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参数资料
| 型号： | DAC5687IPZP |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 0.0104 us SETTLING TIME, 16-BIT DAC, PQFP100 |
| 封装： | GREEN, PLASTIC, HTQFP-100 |
| 文件页数： | 34/79页 |
| 文件大小： | 2490K |
| 代理商： | DAC5687IPZP |
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www.ti.com
SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
1, 4, 7, 9, 12,
AGND
I
Analog ground return
17, 19, 22, 25
2, 3, 8, 10, 14,
AVDD
I
Analog supply voltage
16, 18, 23, 24
BIASJ
13
O
Full-scale output current bias
In PLL clock mode and dual clock modes, provides data input rate clock. In external clock mode,
CLK1
59
I
provides optional input data rate clock to FIFO latch. When the FIFO is disabled, CLK1 is not used
and can be left unconnected.
CLK1C
60
I
Complementary input of CLK1.
External and dual clock mode clock input. In PLL mode, CLK2 is unused and can be left
CLK2
62
I
unconnected.
CLK2C
63
I
Complementary input of CLK2. In PLL mode, CLK2C is unused and can be left unconnected.
CLKGND
58, 64
I
Ground return for internal clock buffer
CLKVDD
61
I
Internal clock buffer supply voltage
34–36, 39–43,
A-channel data bits 0 through 15. DA15 is most significant data bit (MSB). DA0 is least significant
DA[15:0]
I
48–55
data bit (LSB). Order can be reversed by register change.
71–78, 83–87,
B-channel data bits 0 through 15. DB15 is most significant data bit (MSB). DB0 is least significant
DB[15:0]
I
90–92
data bit (LSB). Order can be reversed by register change.
27, 38, 45, 57,
DGND
69, 81, 88, 93,
I
Digital ground return
99
26, 32, 37, 44,
DVDD
56, 68, 82, 89,
I
Digital supply voltage
100
Used as external reference input when internal reference is disabled (i.e., EXTLO connected to
EXTIO
11
I/O
AVDD). Used as internal reference output when EXTLO = AGND, requires a 0.1-
F decoupling
capacitor to AGND when used as reference output
Internal/external reference select. Internal reference selected when tied to AGND, external
EXTLO
15
I/O
reference selected when tied to AVDD. Output only when atest is not zero (register 0x1B bits 7 to
3).
IOUTA1
21
O
A-channel DAC current output. Full scale when all input bits are set 1
IOUTA2
20
O
A-channel DAC complementary current output. Full scale when all input bits are 0
IOUTB1
5
O
B-channel DAC current output. Full scale when all input bits are set 1
IOUTB2
6
O
B-channel DAC complementary current output. Full scale when all input bits are 0
IOGND
47, 79
I
Digital I/O ground return
IOVDD
46, 80
I
Digital I/O supply voltage
LPF
66
I
PLL loop filter connection
Synchronization input signal that can be used to initialize the NCO, coarse mixer, internal clock
PHSTR
94
I
divider, and/or FIFO circuits.
PLLGND
65
I
Ground return for internal PLL
PLLVDD
67
I
PLL supply voltage. When PLLVDD is 0 V, the PLL is disabled.
In PLL mode, provides PLL lock status bit or internal clock signal. PLL is locked to input clock
PLLLOCK
70
O
when high. In external clock mode, provides input rate clock.
When qflag register is 1, the QFLAG pin is used by the user during interleaved data input mode to
QFLAG
98
I
identify the B sample. High QFLAG indicates B sample. Must be repeated every B sample.
RESETB
95
I
Resets the chip when low. Internal pullup
SCLK
29
I
Serial interface clock
SDENB
28
I
Active-low serial data enable, always an input to the DAC5687
Bidirectional serial data in three-pin interface mode, input-only in four-pin interface mode. Three-pin
SDIO
30
I/O
mode is the default after chip reset.
Serial interface data, unidirectional data output, if SDIO is an input. SDO is in the high-impedance
SDO
31
O
state when the three-pin interface mode is selected (register 0x04 bit 7).
4
Copyright 2005–2006, Texas Instruments Incorporated
Product Folder Link(s): DAC5687
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