参数资料
型号: DAC5687IPZP
厂商: TEXAS INSTRUMENTS INC
元件分类: DAC
英文描述: PARALLEL, WORD INPUT LOADING, 0.0104 us SETTLING TIME, 16-BIT DAC, PQFP100
封装: GREEN, PLASTIC, HTQFP-100
文件页数: 25/79页
文件大小: 2490K
代理商: DAC5687IPZP
www.ti.com
Register Name: DAC_CLK_CNTL—Address: 0x1A, Default = 0x00
Register Name: ATEST—Address: 0x1B, Default = 0x00
Register Name: DAC_TEST—Address: 0x1C, Default = 0x00
Address: 0x1D, 0x1E, and 0x1F – Reserved
SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006
BIT 7
BIT 0
Factory use only
0
Reserved for factory use only.
BIT 7
BIT 0
atest(4:0)
phstr_del(1:0)
unused
0
atest(4:0): Can be used to enable clock output at the PLLLOCK pin according to Table 5. Pin EXTLO must be
open when atest(4:0) is not equal to 00000.
Table 5. PLLLOCK Output
atest(4:0)
PLLLOCK Output Signal
PLL Enabled (PLLVDD = 3.3 V)
PLL Disabled (PLLVDD = 0 V)
11101
fDAC
Normal operation
11110
fDAC divided by 2
Normal operation
11111
fDAC divided by 4
Normal operation
All others
Normal operation
phstr_del: Adjusts the initial phase of the fS/2 and fS/4 blocks cmix block after PHSTR.
BIT 7
BIT 0
Factory use only
phstr_clkdiv_sel
0
phstr_clkdiv_sel: Selects the clock used to latch the PHSTR input when restarting the internal dividers. When
set, the full DAC sample rate CLK2 signal latches PHSTR, and when cleared, the divided down input clock
signal latches PHSTR.
Writes have no effect and reads are 0x00.
Copyright 2005–2006, Texas Instruments Incorporated
31
Product Folder Link(s): DAC5687
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