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参数资料
| 型号： | DDC118IRTCT |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 8-CH 20-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQCC48 |
| 封装： | GREEN, PLASTIC, QFN-48 |
| 文件页数： | 14/35页 |
| 文件大小： | 653K |
| 代理商： | DDC118IRTCT |
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DDC118
SBAS325B JUNE 2004 REVISED APRIL 2009
www.ti.com
21
DATA FORMAT (FORMAT)
The serial output data is provided in an offset binary code
as shown in Table 9. The digital input pin FORMAT selects
how many bits are used in the output word. When
FORMAT is high (1), 20 bits are used. When FORMAT is
low (0), the lower 4 bits are truncated so that only 16 bits
are used. Note that the LSB size is 16 times bigger when
FORMAT = 0. An offset is included in the output to allow
slightly negative inputs, from board leakages for example,
from clipping the reading. This offset is approximately
0.4% of the positive full-scale.
Table 9. Ideal Output Code(1) vs Input Signal
INPUT
SIGNAL
IDEAL OUTPUT CODE
FORMAT = HIGH
(1)
IDEAL OUTPUT CODE
FORMAT = LOW
(0)
≥ 100% FS
1111 1111 1111 1111 1111
1111 1111 1111 1111
0.001531% FS
0000 0001 0000 0001 0000
0000 0001 0000 0001
0.001436% FS
0000 0001 0000 0000 1111
0000 0001 0000 0000
0.000191% FS
0000 0001 0000 0000 0010
0000 0001 0000 0000
0.000096% FS
0000 0001 0000 0000 0001
0000 0001 0000 0000
0% FS
0000 0001 0000 0000 0000
0000 0001 0000 0000
0.3955% FS
0000 0000 0000 0000 0000
0000 0000 0000 0000
(1) Excludes the effects of noise, INL, offset, and gain errors.
DATA RETRIEVAL
In both the continuous and non-continuous modes of
operation, the data from the last conversion is available for
retrieval on the falling edge of DVALID (see Figure 20 and
Table 10). Data is shifted out on the falling edge of the data
clock, DCLK. Make sure not to retrieve data while CONV
changes as this can introduce noise. Stop activity on
DCLK at least 10
s before or after a CONV transition.
Setting the FORMAT pin = 0 (16-bit output word) reduces
the time needed to retrieve data by 20%, since there are
fewer bits to shift out. This time reduction can be useful in
multichannel systems requiring only 16 bits of resolution.
CLK
DVALID
DCLK
DOUT
t
18
t
19
t
21
t
20
Input 8
MSB
Input 1
LSB
Input 8
LSB
Input 7
MSB
Input 5
LSB
Input 4
MSB
Input 2
LSB
Input 1
MSB
Input 8
MSB
t
20
Figure 20. Digital Interface Timing Diagram for Data Retrieval From a Single DDC118
Table 10. Timing for the DDC118 Data Retrieval
SYMBOL
DESCRIPTION
CLK = 4MHz, CLK_4X = 0
CLK = 4.8MHz, CLK_4X = 0
UNITS
SYMBOL
DESCRIPTION
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
t18
Propagation Delay from Falling Edge of CLK to DVALID LOW
5
ns
t19
Propagation Delay from Falling Edge of DCLK to DVALID HIGH
5
ns
t20
Hold Time that DOUT is Valid Before the Falling Edge of DVALID
1.75
1.458
s
t21
Hold Time that DOUT is Valid After Falling Edge of DCLK
5
ns
t21A(1)
Propagation Delay from Falling Edge of DCLK to Valid DOUT
10
ns
(1) With a maximum load of one DDC118 (4pF typical) with an additional load of (5pF).
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