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| 型号： | DDC118IRTCT |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 8-CH 20-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQCC48 |
| 封装： | GREEN, PLASTIC, QFN-48 |
| 文件页数： | 7/35页 |
| 文件大小： | 653K |
| 代理商： | DDC118IRTCT |
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DDC118
SBAS325B JUNE 2004 REVISED APRIL 2009
www.ti.com
15
TIMING EXAMPLES
Cont Mode
A few timing diagrams help illustrate the operation of the
state machine. These diagrams are shown in Figure 11
through Figure 19. Table 6 gives generalized timing
specifications in units of CLK periods for CLK_4X = 0. If
CLK_4X = 1, these values increase by a factor of four
because of the internal clock divider. Values (in
s) for
Table 6 can be easily found for a given CLK. For example,
if CLK = 4MHz, then a CLK period = 0.25
s. t6 in Table 6
would then be 367.50
± 0.125s.
Table 6. Timing Specifications Generalized in
CLK Periods
SYMBOL
DESCRIPTION
VALUE
(CLK periods with CLK_4X = 0)
t6
Cont mode m/r/az cycle
1470
± 0.5
t7
Cont mode data ready
1380
± 0.5
t8
1st ncont mode data ready
1379
± 1
t9
2nd ncont mode data ready
1450
t10
Ncont mode m/r/az cycle
2901
± 1
Figure 11 shows a few integration cycles beginning with
initial power-up for a cont mode example. The top signal
is CONV and is supplied by the user. The next line
indicates the current state in the state diagram. The
following two traces show when integrations and
measurement cycles are underway. The internal signal
mbsy is shown next. Finally, DVALID is given. DVALID
goes active low when data is ready to be retrieved from the
DDC118. It stays low until DCLK is taken high and then
back low by the user. The text below the DVALID pulse
indicates the side of the data available to be read, and
arrows help match the data to the corresponding
integration. The signals illustrated in Figure 11 through
Figure 19 are drawn at approximately the same scale.
In Figure 11, the first state is ncont state 8. The DDC118
always powers up in the ncont mode. In this case, the first
state is 8 because CONV is initially low. After the first two
states, cont mode operation is reached and the states
begin toggling between 4 and 5. From now on, the input is
being continuously integrated, either on side A or side B.
The time needed for the m/r/az cycle, or t6, is the same time
that determines the boundary between the cont and ncont
modes described earlier in the Overview section. DVALID
goes low after CONV toggles in time t7, indicating that data
is ready to be retrieved. As shown in Figure 11, there are
two values for t6 and t7. The reason for this is discussed in
the Special Considerations section.
See Figure 12 for the timing diagram of the internal
operations occurring during continuous mode operation.
Table 7 gives the timing specifications in the continuous
mode.
SYMBOL
DESCRIPTION
VALUE (CLK = 4MHz, CLK_4X = 0)
VALUE (CLK = 4.8MHz, CLK_4X = 0)
t6
Cont Mode m/r/az Cycle
367.50
± 0.125s
306.25
± 0.104s
t7
Cont Mode Data Ready
345.00
± 0.125s
287.5
± 0.104s
Figure 11. Continuous Mode Timing
5
6
7
8
45
Integrate A
Integrate B
Integrate A
m/r/az
B
m/r/az A
m/r/az B
CONV
State
Integration
Status
m/r/az
Status
mbsy
DVALID
t6
t7
t= 0
PowerUp
Side B
Data
Side A
Data
Side B
Data
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