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| 型号： | DDC118IRTCT |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 8-CH 20-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQCC48 |
| 封装： | GREEN, PLASTIC, QFN-48 |
| 文件页数： | 4/35页 |
| 文件大小： | 653K |
| 代理商： | DDC118IRTCT |
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DDC118
SBAS325B JUNE 2004 REVISED APRIL 2009
www.ti.com
12
DDC118 Frequency Response
The frequency response of the DDC118 is set by the front
end integrators and is that of a traditional continuous time
integrator, as shown in Figure 7. By adjusting TINT, the
user can change the 3dB bandwidth and the location of the
notches in the response. The frequency response of the
Σ converter that follows the front end integrator is of no
consequence because the converter samples a held
signal from the integrators. That is, the input to the
Σ
converter is always a DC signal. Since the output of the
front end integrators are sampled, aliasing can occur.
Whenever the frequency of the input signal exceeds
one-half of the sampling rate, the signal will fold back down
to lower frequencies.
0
10
20
30
40
50
0.1
T
INT
100
T
INT
1
T
INT
10
T
INT
Frequency
Ga
in
(d
B
)
Figure 7. Frequency Response of the DDC118
Test Mode
When Test Mode is used, the inputs (IN1, IN2, IN3, IN4,
IN5, IN6, IN7, and IN8) are disconnected from the DDC118
integrators to enable the user to measure a zero input
signal regardless of the current supplied to the inputs. In
addition, packets of charge can be transferred to the
integrators in 11pC intervals to measure non-zero values.
The test mode works with both the continuous and
non-continuous modes. The timing diagram for the test
mode is shown in Figure 8 with the timing specifications
given in Table 2.
To enter Test Mode, hold TEST high while CONV
transitions. If TEST is held high during the entire
integration period, the integrators measure a zero value.
This mode can be used to help debug a design or perform
diagnostic tests. To apply packets of charge during Test
Mode, simply strobe TEST low then high before the next
CONV transition. Each rising edge of TEST causes
approximately 11pC of charge to be transferred to the
integrators. This charge transfer is independent of the
integration time. Data retrieval during Test Mode is
identical to normal operation. To exit Test Mode, take
TEST low and allow several cycles after exiting before
using the data.
t
1
t
3
t
4
t
4
t
6
t
5
t
2
Action
CONV
TEST
Integrate B
Integrate A
Test Mode Disabled
0pC into B
11pC into A
22pC into B
33pC into A
Test Mode Disabled
Test Mode Enabled: Inputs Disconnected
Integrate B
Integrate A
Figure 8. Timing Diagram of the Test Mode of the DDC118
Table 2. Timing for the DDC118 in the Test Mode
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t1
Setup Time for Test Mode Enable
100
ns
t2
Setup Time for Test Mode Disable
100
ns
t3
Hold Time for Test Mode Enable
100
ns
t4
From Rising Edge of TEST to the Edge of CONV while Test Mode
Enabled
1
s
t5
Falling Edge to Rising Edge of TEST
1
s
t6
Rising Edge to Falling Edge of TEST
1
s
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