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参数资料
| 型号： | DDC118IRTCT |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 8-CH 20-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQCC48 |
| 封装： | GREEN, PLASTIC, QFN-48 |
| 文件页数： | 9/35页 |
| 文件大小： | 653K |
| 代理商： | DDC118IRTCT |
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DDC118
SBAS325B JUNE 2004 REVISED APRIL 2009
www.ti.com
17
Ncont Mode
Non-continuous mode of operation is intended for Ranges
1 to 7. It is not recommended to use Range 0 when
operating in non-continuous mode. Figure 13 illustrates
operation in the ncont mode. The integrations come in
pairs (that is, sides A/B or sides B/A) followed by a time
during which no integrations occur. During that time, the
previous integrations are being measured, reset and
auto-zeroed. Before the DDC118 can advance to states 3
or 6, both sides A and B must be finished with the m/r/az
cycle which takes time t10. When the m/r/az cycles are
completed, time t11 is needed to prepare the next side for
integration. This time is required for the ncont mode
because the m/r/az cycle of the ncont mode is slightly
different from that of the cont mode. After the first
integration ends, DVALID goes low in time t8. This time is
the same as in the cont mode. The second data will be
ready in time t9 after the first data is ready. One result of the
naming convention used in this data sheet is that when the
DDC118 is operating in the ncont mode, it passes through
both ncont mode states and cont mode states. For
example, in Figure 13, the state pattern is 3, 4, 1, 2, 3, 4,
1, 2, 3, 4 ... where 3 and 4 are cont mode states. Ncont
mode, by definition, means that for some portion of the
time, neither side A nor B is integrating. States that perform
an integration are labeled cont mode states, while those
that do not are called ncont mode states. Since
integrations are performed in the ncont mode, just not
continuously, some cont mode states must be used in a
ncont mode state pattern.
SYMBOL
DESCRIPTION
VALUE (CLK = 4MHz, CLK_4X = 0)
VALUE (CLK = 4.8MHz, CLK_4X = 0)
t8
1st ncont Mode Data Ready
344.75
± 0.25s
287.292
± 0.208s
t9
2nd ncont Mode Data Ready
362.5
s
302.083
s
t10
ncont Mode m/r/az Cycle
725.25
± 0.25s
604.375
± 0.208s
t11
Prepare Side for Integration
≥ 18s
≥ 15s
Figure 13. Non-Continuous Mode Timing
23
1
34
4
1
2
Int B
Int A
Int B
Int A
m/r/az B
m/r/az A
m/r/az B
CONV
State
mbsy
m/r/az
Status
Integration
Status
DVALID
t
10
t
9
t
11
t
8
Side A
Data
Side B
Data
Side A
Data
Side B
Data
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