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参数资料
| 型号： | DK-DEV-2AGX125N |
| 厂商： | Altera |
| 文件页数： | 61/90页 |
| 文件大小： | 0K |
| 描述： | KIT DEV ARRIA II GX FPGA 2AGX125 |
| 产品培训模块： | Arria II GX FPGA Three Reasons to Use FPGA's in Industrial Designs |
| 特色产品： | Arria? II GX FPGA Development Kit |
| 标准包装： | 1 |
| 系列： | Arria II GX |
| 类型： | FPGA |
| 适用于相关产品： | EP2AGX125EF35 |
| 所含物品： | 板，线缆，CD，DVD，电源 |
| 产品目录页面： | 605 (CN2011-ZH PDF) |
| 相关产品： | 544-2599-5-ND - IC ARRIA II GX 125K 1152FBG 544-2598-5-ND - IC ARRIA II GX 125K 1152FBG 544-2597-5-ND - IC ARRIA II GX 125K 1152FBG |
| 其它名称： | 544-2600 |
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1–56
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
December 2013
Altera Corporation
tDLOCK
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
——
1
ms
fCLBW
PLL closed-loop low bandwidth
—
0.3
—
MHz
PLL closed-loop medium bandwidth
—
1.5
—
MHz
PLL closed-loop high bandwidth (7)
—4
—
MHz
tPLL_PSERR
Accuracy of PLL phase shift
—
±50
ps
tARESET
Minimum pulse width on the areset signal
10
—
ns
Input clock cycle to cycle jitter (FREF ≥ 100 MHz)
—
0.15
UI (p-p)
Input clock cycle to cycle jitter (FREF < 100 MHz)
—
±750
ps (p-p)
tOUTPJ_DC (5)
Period Jitter for dedicated clock output (FOUT ≥ 100 MHz)
—
175
ps (p-p)
Period Jitter for dedicated clock output (FOUT < 100 MHz)
—
17.5
mUI (p-p)
tOUTCCJ_DC (5)
Cycle to Cycle Jitter for dedicated clock output
(FOUT ≥ 100 MHz)
—
175
ps (p-p)
Cycle to Cycle Jitter for dedicated clock output
(FOUT < 100 MHz)
—
17.5
mUI (p-p)
tOUTPJ_IO (5),
Period Jitter for clock output on regular I/O
(FOUT ≥ 100 MHz)
—
600
ps (p-p)
Period Jitter for clock output on regular I/O
(FOUT < 100 MHz)
—
60
mUI (p-p)
tOUTCCJ_IO (5),
Cycle to Cycle Jitter for clock output on regular I/O
(FOUT ≥ 100 MHz)
—
600
ps (p-p)
Cycle to Cycle Jitter for clock output on regular I/O
(FOUT < 100 MHz)
—
60
mUI (p-p)
tCASC_OUTPJ_DC
Period Jitter for dedicated clock output in cascaded PLLs
(FOUT ≥100MHz)
—
250
ps (p-p)
Period Jitter for dedicated clock output in cascaded PLLs
(FOUT < 100MHz)
—
25
mUI (p-p)
fDRIFT
Frequency drift after PFDENA is disabled for duration of
100 us
—
±10
%
Notes to Table 1–45:
(1) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(2) This specification is limited by the lower of the two: I/O FMAX or FOUT of the PLL.
(3) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source that is less
than 120 ps.
(4) FREF is fIN/N when N = 1.
(5) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a
different measurement method and are available in Table 1–64 on page 1–71.
(6) The cascaded PLL specification is only applicable with the following condition:
a. Upstream PLL: 0.59 Mhz
Upstream PLL BW < 1 MHz
b. Downstream PLL: Downstream PLL BW > 2 MHz
(7) High bandwidth PLL settings are not supported in external feedback mode.
(8) External memory interface clock output jitter specifications use a different measurement method, which is available in Table 1–63 on
Table 1–45. PLL Specifications for Arria II GZ Devices (Part 2 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
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