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| 型号： | DK-START-3C25N |
| 厂商： | Altera |
| 文件页数： | 25/34页 |
| 文件大小： | 0K |
| 描述： | KIT STARTER CYCLONE III EP3C25 |
| 产品培训模块： | Cyclone® III FPGA Three Reasons to Use FPGA's in Industrial Designs |
| 特色产品： | Cyclone? III FPGA Starter Kit |
| 标准包装： | 1 |
| 系列： | Cyclone® III |
| 类型： | FPGA |
| 适用于相关产品： | EP3C25 |
| 所含物品： | 开发板、Quartus?II 网络版、用户指南、参考手册、示意图、布局、BOM 等 |
| 产品目录页面： | 605 (CN2011-ZH PDF) |
| 相关产品： | EP3C25F256C7N-ND - IC CYCLONE III FPGA 256-FBGA 544-2565-ND - IC CYCLONE III FPGA 25K 324 FBGA EP3C25E144I7-ND - IC CYCLONE III FPGA 25K 144 EQFP EP3C25F256I7-ND - IC CYCLONE III FPGA 25K 256 FBGA EP3C25F324I7-ND - IC CYCLONE III FPGA 25K 324 FBGA EP3C25U256I7-ND - IC CYCLONE III FPGA 25K 256 UBGA 544-2546-ND - IC CYCLONE III FPGA 25K 256 UBGA 544-2545-ND - IC CYCLONE III FPGA 25K 256 UBGA 544-2544-ND - IC CYCLONE III FPGA 25K 324 FBGA 544-2543-ND - IC CYCLONE III FPGA 25K 256 FBGA 更多... |
| 其它名称： | 544-2370 |
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Chapter 1: Cyclone III Device Datasheet
Switching Characteristics
1–25
Table 1–34. Cyclone III Devices Memory Output Clock Jitter Specifications (1) ,
(2)
(Part 2 of 2)
Parameter
Duty cycle jitter
Symbol
t JIT(duty)
Min
-150
Max
150
Unit
ps
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2 standard.
(2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a global
clock network.
Duty Cycle Distortion Specifications
Table 1–35. Duty Cycle Distortion on Cyclone III Devices I/O Pins
Symbol
C6
C7, I7
C8, A7
Unit
Min
Max
Min
Max
Min
Max
Output Duty Cycle
45
55
45
55
45
55
%
(1) Duty cycle distortion specification applies to clock outputs from PLLs, global clock tree, and IOE driving dedicated
and general purpose I/O pins.
(2) Cyclone III devices meet specified duty cycle distortion at maximum output toggle rate for each combination of
I/O standard and current strength.
OCT Calibration Timing Specification
power-up for Cyclone III devices.
Table 1–36. Cyclone III Devices Timing Specification for Series OCT with Calibration at Device
Power-Up (1)
t OCTCAL
Symbol
Description
Duration of series OCT with
calibration at device power-up
Maximum
20
Unit
μs
(1) OCT calibration takes place after device configuration, before entering user mode.
IOE Programmable Delay
(Part 1 of 2)
Max Offset
Parameter
Paths
Affected
Number
of
Settings
Min
Offset
Fast Corner
Slow Corner
Unit
A7, I7
C6
C6
C7
C8
I7
A7
Input delay from pin to
internal cells
Input delay from pin to
input register
Pad to I/O
dataout to
core
Pad to I/O
input register
7
8
0
0
1.211
1.203
1.314
1.307
2.175
2.19
2.32
2.387
2.386
2.54
2.366
2.43
2.49
2.545
ns
ns
July 2012
Altera Corporation
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