参数资料
型号: DK-START-3C25N
厂商: Altera
文件页数: 33/34页
文件大小: 0K
描述: KIT STARTER CYCLONE III EP3C25
产品培训模块: Cyclone® III FPGA
Three Reasons to Use FPGA's in Industrial Designs
特色产品: Cyclone? III FPGA Starter Kit
标准包装: 1
系列: Cyclone® III
类型: FPGA
适用于相关产品: EP3C25
所含物品: 开发板、Quartus?II 网络版、用户指南、参考手册、示意图、布局、BOM 等
产品目录页面: 605 (CN2011-ZH PDF)
相关产品: EP3C25F256C7N-ND - IC CYCLONE III FPGA 256-FBGA
544-2565-ND - IC CYCLONE III FPGA 25K 324 FBGA
EP3C25E144I7-ND - IC CYCLONE III FPGA 25K 144 EQFP
EP3C25F256I7-ND - IC CYCLONE III FPGA 25K 256 FBGA
EP3C25F324I7-ND - IC CYCLONE III FPGA 25K 324 FBGA
EP3C25U256I7-ND - IC CYCLONE III FPGA 25K 256 UBGA
544-2546-ND - IC CYCLONE III FPGA 25K 256 UBGA
544-2545-ND - IC CYCLONE III FPGA 25K 256 UBGA
544-2544-ND - IC CYCLONE III FPGA 25K 324 FBGA
544-2543-ND - IC CYCLONE III FPGA 25K 256 FBGA
更多...
其它名称: 544-2370
Chapter 1: Cyclone III Device Datasheet
Document Revision History
Table 1–40. Document Revision History (Part 2 of 3)
1–33
Date
Version
Changes
Updated “Operating Conditions” section and included information on automotive device.
Updated Table 1–3, Table 1–6, and Table 1–7, and added automotive information.
Under “Pin Capacitance” section, updated Table 1–9 and Table 1–10.
Added new “Schmitt Trigger Input” section with Table 1–12.
Under “I/O Standard Specifications” section, updated Table 1–13, 1–12 and 1–12.
May 2008
2.0
Under “Switching Characteristics” section, updated Table 1–19, 1–15, 1–16, 1–16, 1–17,
1–18, 1–19, 1–20, 1–21, 1–21, 1–23, 1–23, 1–23, 1–24, and 1–25.
Updated Figure 1–5 and 1–29.
Deleted previous Table 1-35 “DDIO Outputs Half-Period Jitter”.
Under “I/O Timing” section, updated Table 1–38, 1–29, 1–32, 1–33, 1–26, and 1–26.
Under “Typical Design Performance” section updated Table 1–46 through 1–145.
Under “Core Performance Specifications”, updated Tables 1-18 and 1-19.
Under “Preliminary, Correlated, and Final Timing”, updated Table 1-37.
December 2007
1.5
Under “Typical Design Performance”, updated Tables 1-45, 1-46, 1-51, 1-52, 1-57, 1-58,
Tables 1-63 through 1-68. 1-69, 1-70, 1-75, 1-76, 1-81, 1-82, Tables 1-87 through 1-92,
Tables 1-99, 1-100, 1-107, and 1-108.
Updated the C VREFTB value in Table 1-9.
Updated Table 1-21.
Under “High-Speed I/O Specification” section, updated Tables 1-25 through 1-30.
Updated Tables 1-31 through 1-38.
Added new Table 1-32.
October 2007
1.4
Under “Maximum Input and Output Clock Toggle Rate” section, updated Tables 1-40
through 1-42.
Under “IOE Programmable Delay” section, updated Tables 1-43 through 1-44.
Under “User I/O Pin Timing Parameters” section, updated Tables 1-45 through 1-92.
Under “Dedicated Clock Pin Timing Parameters” section, updated Tables 1-93 through 1-
108.
Updated Table 1-1 with V ESDHBM and V ESDCDM information.
Updated R CONF_PD information in Tables 1-10.
July 2007
1.3
Added Note (3 ) to Table 1-12.
Updated t DLOCK information in Table 1-19.
Updated Table 1-43 and Table 1-44.
Added “Document Revision History” section.
June 2007
1.2
Updated Cyclone III graphic in cover page.
July 2012
Altera Corporation
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