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| 型号： | DK-START-3C25N |
| 厂商： | Altera |
| 文件页数： | 26/34页 |
| 文件大小： | 0K |
| 描述： | KIT STARTER CYCLONE III EP3C25 |
| 产品培训模块： | Cyclone® III FPGA Three Reasons to Use FPGA's in Industrial Designs |
| 特色产品： | Cyclone? III FPGA Starter Kit |
| 标准包装： | 1 |
| 系列： | Cyclone® III |
| 类型： | FPGA |
| 适用于相关产品： | EP3C25 |
| 所含物品： | 开发板、Quartus?II 网络版、用户指南、参考手册、示意图、布局、BOM 等 |
| 产品目录页面： | 605 (CN2011-ZH PDF) |
| 相关产品： | EP3C25F256C7N-ND - IC CYCLONE III FPGA 256-FBGA 544-2565-ND - IC CYCLONE III FPGA 25K 324 FBGA EP3C25E144I7-ND - IC CYCLONE III FPGA 25K 144 EQFP EP3C25F256I7-ND - IC CYCLONE III FPGA 25K 256 FBGA EP3C25F324I7-ND - IC CYCLONE III FPGA 25K 324 FBGA EP3C25U256I7-ND - IC CYCLONE III FPGA 25K 256 UBGA 544-2546-ND - IC CYCLONE III FPGA 25K 256 UBGA 544-2545-ND - IC CYCLONE III FPGA 25K 256 UBGA 544-2544-ND - IC CYCLONE III FPGA 25K 324 FBGA 544-2543-ND - IC CYCLONE III FPGA 25K 256 FBGA 更多... |
| 其它名称： | 544-2370 |
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1–26
Chapter 1: Cyclone III Device Datasheet
I/O Timing
Table 1–37. Cyclone III Devices IOE Programmable Delay on Column Pins (1) ,
(2)
(Part 2 of 2)
Max Offset
Parameter
Paths
Affected
Number
of
Settings
Min
Offset
Fast Corner
Slow Corner
Unit
A7, I7
C6
C6
C7
C8
I7
A7
Delay from output
register to output pin
I/O output
register to
pad
2
0
0.479
0.504
0.915
1.011
1.107
1.018
1.048
ns
Input delay from
Pad to global
dual-purpose clock pin
clock
12
0
0.664
0.694
1.199
1.378
1.532
1.392
1.441
ns
to fan-out destinations
network
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting ‘0’ as available in the Quartus II software.
Table 1–38. Cyclone III Devices IOE Programmable Delay on Row Pins
Max Offset
Parameter
Paths
Affected
Number
of
Settings
Min
Offset
Fast Corner
Slow Corner
Unit
A7, I7
C6
C6
C7
C8
I7
A7
Input delay from pin to
internal cells
Input delay from pin to
input register
Delay from output
register to output pin
Input delay from
dual-purpose clock pin
to fan-out destinations
Pad to I/O
dataout to
core
Pad to I/O
input register
I/O output
register to
pad
Pad to global
clock network
7
8
2
12
0
0
0
0
1.209
1.207
0.51
0.669
1.314
1.312
0.537
0.698
2.174
2.202
0.962
1.207
2.335
2.402
1.072
1.388
2.406
2.558
1.167
1.542
2.381
2.447
1.074
1.403
2.505
2.557
1.101
1.45
ns
ns
ns
ns
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting ‘0’ as available in the Quartus II software
I/O Timing
You can use the following methods to determine the I/O timing:
■
■
the Excel-based I/O Timing.
the Quartus II timing analyzer.
The Excel-based I/O Timing provides pin timing performance for each device density
and speed grade. The data is typically used prior to designing the FPGA to get a
timing budget estimation as part of the link timing analysis. The Quartus II timing
analyzer provides a more accurate and precise I/O timing data based on the specifics
of the design after place-and-route is complete.
July 2012 Altera Corporation
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