参数资料
型号: DK-START-3C25N
厂商: Altera
文件页数: 29/34页
文件大小: 0K
描述: KIT STARTER CYCLONE III EP3C25
产品培训模块: Cyclone® III FPGA
Three Reasons to Use FPGA's in Industrial Designs
特色产品: Cyclone? III FPGA Starter Kit
标准包装: 1
系列: Cyclone® III
类型: FPGA
适用于相关产品: EP3C25
所含物品: 开发板、Quartus?II 网络版、用户指南、参考手册、示意图、布局、BOM 等
产品目录页面: 605 (CN2011-ZH PDF)
相关产品: EP3C25F256C7N-ND - IC CYCLONE III FPGA 256-FBGA
544-2565-ND - IC CYCLONE III FPGA 25K 324 FBGA
EP3C25E144I7-ND - IC CYCLONE III FPGA 25K 144 EQFP
EP3C25F256I7-ND - IC CYCLONE III FPGA 25K 256 FBGA
EP3C25F324I7-ND - IC CYCLONE III FPGA 25K 324 FBGA
EP3C25U256I7-ND - IC CYCLONE III FPGA 25K 256 UBGA
544-2546-ND - IC CYCLONE III FPGA 25K 256 UBGA
544-2545-ND - IC CYCLONE III FPGA 25K 256 UBGA
544-2544-ND - IC CYCLONE III FPGA 25K 324 FBGA
544-2543-ND - IC CYCLONE III FPGA 25K 256 FBGA
更多...
其它名称: 544-2370
Chapter 1: Cyclone III Device Datasheet
Glossary
Table 1–39. Glossary (Part 3 of 5)
1–29
Letter
Term
V OH
Definitions
V IH(DC)
V IH (AC )
V CCIO
Single-ended
Voltage
V REF
V IL(DC)
V IL(AC )
S
referenced I/O
Standard
V OL
V SS
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal
values. The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input crosses the AC value, the receiver
changes to the new logic state. The new logic state is then maintained as long as the input stays
beyond the DC threshold. This approach is intended to provide predictable receiver timing in the
presence of input waveform ringing .
SW (Sampling
Window)
t C
TCCS (Channel-
to-channel-skew)
tcin
t CO
tcout
t DUTY
HIGH-SPEED I/O Block: The period of time during which the data must be valid to capture it
correctly. The setup and hold times determine the ideal strobe position in the sampling window.
High-speed receiver/transmitter input and output clock period.
HIGH-SPEED I/O Block: The timing difference between the fastest and slowest output edges,
including t CO variation and clock skew. The clock is included in the TCCS measurement.
Delay from clock pad to I/O input register.
Delay from clock pad to I/O output.
Delay from clock pad to I/O output register.
HIGH-SPEED I/O Block: Duty cycle on high-speed transmitter output clock.
T
July 2012
t FALL
t H
Timing Unit
Interval (TUI)
t INJITTER
t OUTJITTER_DEDCLK
t OUTJITTER_IO
tpllcin
tpllcout
Altera Corporation
Signal High-to-low transition time (80–20%).
Input register hold time.
HIGH-SPEED I/O block: The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t C /w).
Period jitter on PLL clock input.
Period jitter on dedicated clock output driven by a PLL.
Period jitter on general purpose I/O driven by a PLL.
Delay from PLL inclk pad to I/O input register.
Delay from PLL inclk pad to I/O output register.
相关PDF资料
PDF描述
DK-START-4CGX15N KIT STARTER CYCLONE IV GX
DK-V5-EMBD-ML507-G-J DEV KIT V5 W/ISM & EDK JAPAN
DK-V6-EMBD-G-XP1 DEV KIT EMBEDDED VIRTEX 6
DK-VIDEO-2C70N VIDEO KIT W/CYCLONE II EP2C70N
DK-VIDEO-4SGX230N VIDEO KIT STRATIX IV EP4SGX230
相关代理商/技术参数
参数描述
DK-START-4CGX15N 功能描述:可编程逻辑 IC 开发工具 FPGA Starter Kit For EP4CGX15BF14 RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压:
DK-START-4CGX15N/P 制造商:Altera Corporation 功能描述:KIT STARTER CYCLONE IV GX TRX PROMO
DK-START-5AGXB3N 功能描述:可编程逻辑 IC 开发工具 FPGA Development Kit For 5AGXFB3H4F35C5N RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压:
DK-START-5AGXB3NES 功能描述:可编程逻辑 IC 开发工具 FPGA Starter Kit For 5AGXFB3H4F RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压:
DKTA-620 功能描述:测试配件 - 其他 DUAL TYPE K THERMOCOUPLE ADAPTER RoHS:否 制造商:Tektronix 附件类型:Soft Case 颜色:Gray 设备类型:Transit Case 产品:Accessories