参数资料
型号: DR-TRC103-950-DK
厂商: RFM
文件页数: 22/65页
文件大小: 0K
描述: KIT DEV 950MHZ RFIC SRR
标准包装: 1
类型: 收发器,SRR
频率: 950MHz ~ 960MHz
适用于相关产品: TRC103-950
已供物品: 2 个板,天线,电池,线缆,CD,电源适配器
3.9.4 Packet Payload Processing in Transmit and Receive
The TRC103 packet handler constructs transmit packets using the payload bytes in the FIFO. In receive, it pro-
cesses the packets and extracts the payload bytes to the FIFO. Packet processing in transmit and receive are
detailed below.
For transmit, the packet handler adds the following fields and processing to the payload in the FIFO:
1. One to four programmable preamble bytes
2. One to four start pattern bytes, programmable and usually set to at least 2 bytes
3. Optional CRC checksum calculated over the FIFO payload and appending to the end of the packet
4. Optional Manchester encoding or DC-balanced scrambling
The payload in the FIFO may contain one or both of the following optional fields:
1. A length byte if the variable packet length mode is selected
2. A node address byte
The way transmission is initiated depends on the configuration set by the user and the value of the
IRQCFG0E_Start_Full[4] bit.
If the FIFO is filled while transmit mode is enabled, and if IRQCFG0E_Start_Full[4] is set to 1, the modulator
waits until the first byte is written into the FIFO, then it starts sending the programmed preamble bytes followed by
the start pattern and the user payload. If IRQCFG0E_Start_Full[4 ] is set to 0 in the same conditions, the modu-
lator waits until the number of bytes written in the FIFO is equal to the number defined in the register MCFG05_
FIFO_thresh[5..0] . Note that the transmitter automatically sends preamble bytes in addition the number pro-
grammed while in transmit mode and waiting for the FIFO to receive the required number of bytes to start data
transmission. Data to be transmitted can also be written into the FIFO during standby mode. In this case, the data
is automatically transmitted when the transmit mode is enabled and the transmitter reaches its steady state.
If CRC is enabled, the CRC checksum is calculated over the payload bytes. This 16-bit checksum is sent after the
bytes in the FIFO. If CRC is enabled, the TX_STOP bit is set when the last CRC bit is transferred to the TX modu-
lator. If CRC is not enabled, the TX_STOP bit is set when the last bit from the FIFO is transferred to the TX modu-
lator. Note that the transmitter must remain on one bit period after the TX_STOP bit is set while the last bit is be-
ing transmitted. If the transmitter remains on following the transmission of the last bit after TX_STOP is set, the
transmitter will send preamble bytes. If Manchester encoding or scrambling is enabled, all data except the pream-
ble and start pattern is encoded or scrambled before transmission. Note that the length byte in the FIFO deter-
mines the length of the packet to be sent and the PKTCFG1C_Pkt_len[6..0] parameter is not used in transmit.
In receive the packet handler retrieves the payload by performing the following steps:
1. Data and clock recovery synchronization to the preamble
2. Start pattern detection
3. Optional address byte check
4. Error detection through CRC
When receive mode is enabled, the demodulator detects the preamble followed by the start pattern. If fixed length
packet format is enabled, then the number of bytes received as the payload is given by the PKTCFG1C_Pkt_
len[6..0] parameter.
In variable length and extended variable length packet modes, the first byte received after the start pattern
is interpreted as the length of the balance of the payload. An internal length counter is initialized to this length.
The PKTCFG1C_Pkt_len[6..0] register must be set to a value which is equal to or greater than the maximum
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Page 22 of 65
TRC103 - 11/29/12
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