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参数资料
| 型号： | DR-TRC103-950-DK |
| 厂商： | RFM |
| 文件页数： | 58/65页 |
| 文件大小： | 0K |
| 描述： | KIT DEV 950MHZ RFIC SRR |
| 标准包装： | 1 |
| 类型： | 收发器，SRR |
| 频率： | 950MHz ~ 960MHz |
| 适用于相关产品： | TRC103-950 |
| 已供物品： | 2 个板，天线，电池，线缆，CD，电源适配器 |
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Generation of a 16-bit error detection CRC
Optional 1-byte node address and/or 1-byte length address
Recognition of start pattern in receive mode
Automatic removal of preamble and start pattern in receive mode (payload only in FIFO)
Flagging of received packets with errors or flagging and discard of packets with errors
Filtering of received packets based on address byte - address match only, address byte plus 0x00
broadcast address or address byte plus 0x00 and 0xFF broadcast addresses
New IRQ0 and IRQ1 mapping options
The SPI interface is used with Packet data mode as with Buffered data mode. IRQ0 and IRQ1 mapping is config-
ured in register IRQCFG0D . Bits 7..6 select the signal for IRQ0 in the receive mode. In transmit mode, IRQ0
mapping is set by IRQCFG0E bit 4. IRQCFG0D bits 5..4 select the signal for IRQ1 in the receive mode. Bit 3 se-
lects the IRQ1 signal in transmit mode. The mapping options for Packet data mode are summarized in Table 76
below:
IRQCFG0D bits
7..6
7..6
7..6
7..6
3
3
5..4
5..4
5..4
5..4
3
3
Cfg
00
01
10
11
X
X
00
01
10
11
0
1
State
RX
RX
RX
RX
TX
TX
RX
RX
RX
RX
TX
TX
IRQ
0
0
0
0
0
0
1
1
1
1
1
1
Source
Data_Rdy (CRC OK)
Write_byte (high pulse when received byte written to FIFO)
nFIFOEMPY (low when FIFO is empty)
Start Pattern Detect (ADDRS_cmp = 0)
or Node Address Match (ADDRS_cmp = 1)
FIFO_Int_Tx (FIFO_thres) if Start_Full = 0
nFIFOEMPY if Start_Full = 1
CRC_OK
FIFOFULL
RSSI_IRQ
FIFO_Int_Rx (FIFO_thres)
FIFOFULL
TX_STOP
Table 76
In addition, IRQCFG0E allows several internal FIFO interrupts to be configured. These are summarized in Table
77 below:
IRQCFG0E bits
7
7
6
6
5
5
4
4
3
3
2
2
Cfg
0
1
0
1
0
1
0
1
0
1
1
0
FIFO Control
Start FIFO fill when Start Pattern detected
Control FIFO with bit 6
Stop filling FIFO (if bit 7 is 0, this is Start Pattern Detect)
Start filling FIFO
Transmitting all pending bits in FIFO
All bits in FIFO transmitted
Start transmission when FIFO at or above threshold0
Start transmission if nFIFOEMPY = 1 (not empty)
Disable RSSI interrupt (bit 2)
Enable RSSI interrupt (bit 2)
RF signal ≥ RSSI threshold
RF signal < RSSI Threshold
Table 77
www.RFM.com E-mail: info@rfm.com
? 2009-2010 by RF Monolithics, Inc.
Technical support +1.800.704.6079
Page 58 of 65
TRC103 - 11/29/12
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| DR-TRC105-304-EV | 功能描述:射频开发工具 TRC105 Evaluation Board 303-307 MHz RoHS:否 制造商:Taiyo Yuden 产品:Wireless Modules 类型:Wireless Audio 工具用于评估:WYSAAVDX7 频率: 工作电源电压:3.4 V to 5.5 V |
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