- 您现在的位置：买卖IC网 > PDF目录97867 > DS21FF44N (DALLAS SEMICONDUCTOR) DATACOM, FRAMER, PBGA300 PDF资料下载
参数资料
| 型号： | DS21FF44N |
| 厂商： | DALLAS SEMICONDUCTOR |
| 元件分类： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PBGA300 |
| 封装： | 27 X 27 MM, BGA-300 |
| 文件页数： | 47/110页 |
| 文件大小： | 526K |
| 代理商： | DS21FF44N |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页当前第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页
DS21FT44/DS21FF44
41 of 110
11.
STATUS AND INFORMATION REGISTERS
There is a set of seven registers per framer that contain information on the current real time status of a
framer in the DS21Q44, Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register
(RIR), Synchronizer status Register (SSR) and a set of three registers for the onboard HDLC controller.
The specific details on the four registers pertaining to the HDLC controller are covered in Section 19 but
they operate the same as the other status registers in the DS21Q44 and this operation is described below.
When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers
will be set to a one. All of the bits in SR1, SR2, and RIR1 registers operate in a latched fashion. The
Synchronizer status Register contents are not latched. This means that if an event or an alarm occurs and
a bit is set to a one in any of the registers, it will remain set until the user reads that bit. The bit will be
cleared when it is read and it will not be set again until the event has occurred again (or in the case of the
RSA1, RSA0, RDMA, RUA1, RRA, RCL, and RLOS alarms, the bit will remain set if the alarm is still
present).
The user will always precede a read of any of the SR1, SR2 and RIR registers with a write. The byte
written to the register will inform the framer which bits the user wishes to read and have cleared. The
user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and
a zero in the bit positions he or she does not wish to obtain the latest information on. When a one is
written to a bit location, the read register will be updated with the latest information. When a zero is
written to a bit position, the read register will not be updated and the previous value will be held. A write
to the status and information registers will be immediately followed by a read of the same register. The
read result should be logically AND’ed with the mask byte that was just written and this value should be
written back into the same register to insure that bit does indeed clear.
This second write step is
necessary because the alarms and events in the status registers occur asynchronously in respect to their
access via the parallel port.
This write–read– write scheme allows an external microcontroller or
microprocessor to individually poll certain bits without disturbing the other bits in the register. This
operation is key in controlling the DS21Q44 with higher–order software languages.
The SSR register operates differently than the other three. It is a read only register and it reports the
status of the synchronizer in real time. This register is not latched and it is not necessary to precede a
read of this register with a write.
The SR1, SR2, and HSR registers have the unique ability to initiate a hardware interrupt via the INT*
output pin. Each of the alarms and events in the SR1, SR2, and HSR can be either masked or unmasked
from the interrupt pin via the Interrupt Mask Register 1 (IMR1), Interrupt Mask Register 2 (IMR2), and
HDLC Interrupt Mask Register (HIMR) respectively. The HIMR register is covered in Section 19.
The interrupts caused by four of the alarms in SR1 (namely RUA1, RRA, RCL, and RLOS) act
differently than the interrupts caused by other alarms and events in SR1 and SR2 (namely RSA1, RDMA,
RSA0, RSLIP, RMF, RAF, TMF, SEC, TAF, LOTC, RCMF, and TSLIP). These four alarm interrupts
will force the INT* pin low whenever the alarm changes state (i.e., the alarm goes active or inactive
according to the set/clear criteria in Table 11-1). The INT* pin will be allowed to return high (if no other
interrupts are present) when the user reads the alarm bit that caused the interrupt to occur. If the alarm is
still present, the register bit will remain set.
The event caused interrupts will force the INT* pin low when the event occurs. The INT* pin will be
allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the
interrupt to occur.
相关PDF资料 |
PDF描述 |
|---|---|
| DS21FT40N | DATACOM, FRAMER, PBGA300 |
| DS21FT40 | DATACOM, FRAMER, PBGA300 |
| DS21FT42 | DATACOM, FRAMER, PBGA300 |
| DS21FT42N | DATACOM, FRAMER, PBGA300 |
| DS21FF42 | DATACOM, FRAMER, PBGA300 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS21FT40 | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:Four x Three 12 Channel E1 Framer |
| DS21FT40N | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| DS21FT42 | 功能描述:网络控制器与处理器 IC 4x4 16/4x3 12 Chnl T1/T1 Framer RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21FT42N | 功能描述:网络控制器与处理器 IC 4x4 16/4x3 12 Chnl T1/T1 Framer RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21FT44 | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
发布紧急采购，3分钟左右您将得到回复。