参数资料
型号: DS21FF44N
厂商: DALLAS SEMICONDUCTOR
元件分类: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA300
封装: 27 X 27 MM, BGA-300
文件页数: 73/110页
文件大小: 526K
代理商: DS21FF44N
DS21FT44/DS21FF44
65 of 110
SYMBOL
POSITION
NAME AND DESCRIPTION
1=insert data from the TSa5 register into the transmit data
stream.
Sa6
TSaCR.2
Additional Bit 6 Insertion Control Bit.
0=do not insert data from the TSa6 register into the transmit
data stream.
1=insert data from the TSa6 register into the transmit data
stream.
Sa7
TSaCR.1
Additional Bit 7 Insertion Control Bit.
0=do not insert data from the TSa7 register into the transmit
data stream.
1=insert data from the TSa7 register into the transmit data
stream.
Sa8
TSaCR.0
Additional Bit 8 Insertion Control Bit.
0=do not insert data from the TSa8 register into the transmit
data stream.
1=insert data from the TSa8 register into the transmit data
stream.
19.
HDLC Controller for the Sa Bits or DS0
Each framer in the DS21Q44 has the ability to extract/insert data from/ into the Sa bit positions (Sa4 to
Sa8) or from/to any multiple of DS0 channels Each framer contains a complete HDLC controller and this
operation is covered in Section 19.1.
19.1. GENERAL OVERVIEW
Each framer contains a complete HDLC controller with 64–byte buffers in both the transmit and receive
directions. The HDLC controller performs all the necessary overhead for generating and receiving a
HDLC formatted message.
The HDLC controller automatically generates and detects flags, generates and checks the CRC check
sum, generates and detects abort sequences, stuffs and destuffs zeros (for transparency), and byte aligns
to the HDLC data stream.
There are eleven registers that the host will use to operate and control the operation of the HDLC
controller. A brief description of the registers is shown in Table 19-1.
HDLC CONTROLLER REGISTER LIST Table 19-1
NAME
FUNCTION
HDLC Control Register (HCR)
general control over the HDLC controller
HDLC Status Register (HSR)
key status information for both transmit and receive
directions
HDLC Interrupt Mask Register (HIMR)
allows/stops status bits to/from causing an interrupt
Receive HDLC Information Register
(RHIR)
status information on receive HDLC controller
相关PDF资料
PDF描述
DS21FT40N DATACOM, FRAMER, PBGA300
DS21FT40 DATACOM, FRAMER, PBGA300
DS21FT42 DATACOM, FRAMER, PBGA300
DS21FT42N DATACOM, FRAMER, PBGA300
DS21FF42 DATACOM, FRAMER, PBGA300
相关代理商/技术参数
参数描述
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