参数资料
型号: DS21FF44N
厂商: DALLAS SEMICONDUCTOR
元件分类: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA300
封装: 27 X 27 MM, BGA-300
文件页数: 55/110页
文件大小: 526K
代理商: DS21FF44N
DS21FT44/DS21FF44
49 of 110
EBCR1: E–BIT COUNT REGISTER 1 (Address=04 Hex)
EBCR2: E–BIT COUNT REGISTER 2 (Address=05 Hex)
(MSB)
(LSB)
(note 1)
EB9
EB8
EBCR1
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
EBCR2
SYMBOL
POSITION
NAME AND DESCRIPTION
EB9
EBCR1.1
MSB of the 10–Bit E–Bit Error Count
EB0
EBCR2.0
LSB of the 10–Bit E–Bit Error Count
NOTE:
The upper 6 bits of EBCR1 at address 04 are the least significant bits of the 12–bit FAS error counter.
FAS Error Counter
FAS Count Register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word
of a 12–bit counter that records word errors in the Frame Alignment Signal in timeslot 0. This counter is
disabled when RLOS is high. FAS errors will not be counted when the framer is searching for FAS
alignment and/or synchronization at either the CAS or CRC4 multiframe level. Since the maximum FAS
word error count in a one second period is 4000, this counter cannot saturate.
FASCR1: FAS ERROR COUNT REGISTER 1 (Address=02 Hex)
FASCR2: FAS ERROR COUNT REGISTER 2 (Address=04 Hex)
(MSB)
(LSB)
FAS11
FAS10
FAS9
FAS8
FAS7
FAS6
(note 2)
FASCR1
FAS5
FAS4
FAS3
FAS2
FAS1
FAS0
(note 1)
FASCR2
SYMBOL
POSITION
NAME AND DESCRIPTION
FAS11
FASCR1.7
MSB of the 12–Bit FAS Error Count
FAS0
FASCR2.2
LSB of the 12–Bit FAS Error Count
NOTES:
1. The lower 2 bits of FASCR1 at address 02 are the most significant bits of the 10–bit CRC4 error
counter.
2. The lower 2 bits of FASCR2 at address 04 are the most significant bits of the 10–bit E–Bit counter.
13.
DS0 MONITORING FUNCTION
Each framer in the DS21Q44 has the ability to monitor one DS0 64 Kbps channel in the transmit
direction and one DS0 channel in the receive direction at the same time. In the transmit direction the user
will determine which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the CCR4
register. In the receive direction, the RCM0 to RCM4 bits in the CCR5 register need to be properly set.
The DS0 channel pointed to by the TCM0 to TCM4 bits will appear in the Transmit DS0 Monitor
(TDS0M) register and the DS0 channel pointed to by the RCM0 to RCM4 bits will appear in the Receive
DS0 (RDS0M) register. The TCM4 to TCM0 and RCM4 to RCM0 bits should be programmed with the
decimal decode of the appropriate E1 channel. Channels 1 through 32 map to register values 0 through
31.
相关PDF资料
PDF描述
DS21FT40N DATACOM, FRAMER, PBGA300
DS21FT40 DATACOM, FRAMER, PBGA300
DS21FT42 DATACOM, FRAMER, PBGA300
DS21FT42N DATACOM, FRAMER, PBGA300
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