参数资料
型号: DS21FF44N
厂商: DALLAS SEMICONDUCTOR
元件分类: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA300
封装: 27 X 27 MM, BGA-300
文件页数: 77/110页
文件大小: 526K
代理商: DS21FF44N
DS21FT44/DS21FF44
69 of 110
SYMBOL
POSITION
NAME AND DESCRIPTION
RPS
HSR.5
Receive Packet Start. Set when the HDLC controller detects
an opening byte. The setting of this bit prompts the user to
read the RHIR register for details.
RHALF
HSR.4
Receive FIFO Half Full. Set when the receive 64 byte FIFO
fills beyond the half way point. The setting of this bit prompts
the user to read the RHIR register for details.
RNE
HSR.3
Receive FIFO Not Empty. Set when the receive 64 byte
FIFO has at least 1 byte available for a read. The setting of
this bit prompts the user to read the RHIR register for details.
THALF
HSR.2
Transmit FIFO Half Empty. Set when the transmit 64 byte
FIFO empties beyond the half way point. The setting of this
bit prompts the user to read the THIR register for details.
TNF
HSR.1
Transmit FIFO Not Full. Set when the transmit 64 byte
FIFO has at least 1 byte available. The setting of this bit
prompts the user to read the THIR register for details.
TMEND
HSR.0
Transmit Message End. Set when the transmit HDLC
controller has finished sending a message. The setting of this
bit prompts the user to read the THIR register for details.
NOTE:
The RPE, RPS, and TMEND bits are latched and will be cleared when read.
HIMR: HDLC INTERRUPT MASK REGISTER (Address=B2 Hex)
(MSB)
(LSB)
RPE
RPS
RHALF
RNE
THALF
TNF
TMEND
SYMBOL
POSITION
NAME AND DESCRIPTION
–HIMR.7
Not Assigned. Should be set to zero.
RPE
HIMR.6
Receive Packet End.
0 = interrupt masked.
1 = interrupt enabled.
RPS
HIMR.5
Receive Packet Start.
0 = interrupt masked.
1 = interrupt enabled.
RHALF
HIMR.4
Receive FIFO Half Full.
0 = interrupt masked.
1 = interrupt enabled.
RNE
HIMR.3
Receive FIFO Not Empty.
0 = interrupt masked.
1 = interrupt enabled.
THALF
HIMR.2
Transmit FIFO Half Empty.
0 = interrupt masked.
1 = interrupt enabled.
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