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参数资料
| 型号： | DS21FF44N |
| 厂商： | DALLAS SEMICONDUCTOR |
| 元件分类： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PBGA300 |
| 封装： | 27 X 27 MM, BGA-300 |
| 文件页数： | 83/110页 |
| 文件大小： | 526K |
| 代理商： | DS21FF44N |
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DS21FT44/DS21FF44
74 of 110
SYMBOL
POSITION
NAME AND DESCRIPTION
TDB3
TDC2.2
DS0 Bit 3 Suppress Enable. Set to one to stop this bit from
being used.
TDB2
TDC2.1
DS0 Bit 2 Suppress Enable. Set to one to stop this bit from
being used.
TDB1
TDC2.0
DS0 Bit 1 Suppress Enable. LSB of the DS0. Set to one to
stop this bit from being used.
20.
INTERLEAVED PCM BUS OPERATION
In many architectures, the outputs of individual framers are combined into higher speed serial buses to
simplify transport across the system. The DS21Q44 can be configured to allow each framer’s data and
signaling busses to be multiplexed into higher speed data and signaling busses eliminating external
hardware saving board space and cost.
The interleaved PCM bus option supports two bus speeds and interleave modes. The 4.096 MHz bus
speed allows two framers to share a common bus. The 8.192 MHz bus speed allows all four of the
DS21Q44’s framers to share a common bus. Framers can interleave their data either on byte or frame
boundaries. Framers that share a common bus must be configured through software and require several
device pins to be connected together externally (see figures 20-1 & 20-2). Each framer’s elastic stores
must be enabled and configured for 2.048 MHz operation. The signal RSYNC must be configured as an
input on each framer.
For all bus configurations, one framer will be configured as the master device and the remaining framers
on the shared bus will be configured as slave devices. Refer to the IBO register description below for
more detail. In the 4.096 MHz bus configuration there is one master and one slave per bus. Figure 20-1
shows the DS21Q44 configured to support two 4.096 MHz buses. Bus 1 consists of framers 0 and 1. Bus
2 consists of framers 2 and 3. Framers 0 and 2 are programmed as master devices. Framers 1 and 3 are
programmed as slave devices. In the 8.192 MHz bus configuration there is one master and three slaves.
Figure 20-2 shows the DS21Q44 configured to support a 8.192 MHz bus. Framer 0 is programmed as the
master device. Framers 1, 2 and 3 are programmed as slave devices. Consult timing diagrams in section
22 for additional information.
When using the frame interleave mode, all framers that share an interleaved bus must have receive signals
(RPOS & RNEG) that are synchronous with each other. The received signals must originate from the
same clock reference. This restriction does not apply in the byte interleave mode.
IBO: INTERLEAVE BUS OPERATION REGISTER (Address = B5 Hex)
(MSB)
(LSB)
–
IBOEN
INTSEL
MSEL0
MSEL1
SYMBOL
POSITION
NAME AND DESCRIPTION
–IBO.7
Not Assigned. Should be set to 0.
–IBO.6
Not Assigned. Should be set to 0.
–IBO.5
Not Assigned. Should be set to 0.
–IBO.4
Not Assigned. Should be set to 0.
相关PDF资料 |
PDF描述 |
|---|---|
| DS21FT40N | DATACOM, FRAMER, PBGA300 |
| DS21FT40 | DATACOM, FRAMER, PBGA300 |
| DS21FT42 | DATACOM, FRAMER, PBGA300 |
| DS21FT42N | DATACOM, FRAMER, PBGA300 |
| DS21FF42 | DATACOM, FRAMER, PBGA300 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS21FT40 | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:Four x Three 12 Channel E1 Framer |
| DS21FT40N | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| DS21FT42 | 功能描述:网络控制器与处理器 IC 4x4 16/4x3 12 Chnl T1/T1 Framer RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21FT42N | 功能描述:网络控制器与处理器 IC 4x4 16/4x3 12 Chnl T1/T1 Framer RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21FT44 | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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