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DS21FT44/DS21FF44
43 of 110
RIR: RECEIVE INFORMATION REGISTER (Address=08 Hex)
(MSB)
(LSB)
TESF
TESE
LORC
RESF
RESE
CRCRC
FASRC
CASRC
SYMBOL
POSITION
NAME AND DESCRIPTION
TESF
RIR.7
Transmit Side Elastic Store Full. Set when the transmit side
elastic store buffer fills and a frame is deleted.
TESE
RIR.6
Transmit Side Elastic Store Empty. Set when the transmit
side elastic store buffer empties and a frame is repeated.
LORC
RIR.5
Loss of Receive Clock. Set when the RCLK pin has not
transitioned for at least 2
s (3s ± 1s).
RESF
RIR.4
Receive Side Elastic Store Full. Set when the receive side
elastic store buffer fills and a frame is deleted.
RESE
RIR.3
Receive Side Elastic Store Empty. Set when the receive side
elastic store buffer empties and a frame is repeated.
CRCRC
RIR.2
CRC Resync Criteria Met. Set when 915/1000 code words
are received in error.
FASRC
RIR.1
FAS Resync Criteria Met. Set when 3 consecutive FAS
words are received in error.
CASRC
RIR.0
CAS Resync Criteria Met. Set when 2 consecutive CAS MF
alignment words are received in error.
SSR: SYNCHRONIZER STATUS REGISTER (Address=1E Hex)
(MSB)
(LSB)
CSC5
CSC4
CSC3
CSC2
CSC0
FASSA
CASSA
CRC4SA
SYMBOL
POSITION
NAME AND DESCRIPTION
CSC5
SSR.7
CRC4 Sync Counter Bit 5. MSB of the 6–bit counter.
CSC4
SSR.6
CRC4 Sync Counter Bit 4.
CSC3
SSR.5
CRC4 Sync Counter Bit 3.
CSC2
SSR.4
CRC4 Sync Counter Bit 2.
CSC0
SSR.3
CRC4 Sync Counter Bit 0. LSB of the 6–bit counter. The
next to LSB is not accessible.
FASSA
SSR.2
FAS Sync Active. Set while the synchronizer is searching for
alignment at the FAS level.
CASSA
SSR.1
CAS MF Sync Active. Set while the synchronizer is
searching for the CAS MF alignment word.
CRC4SA
SSR.0
CRC4 MF Sync Active. Set while the synchronizer is
searching for the CRC4 MF alignment word.
CRC4 SYNC COUNTER
The CRC4 Sync Counter increments each time the 8 ms CRC4 multiframe search times out. The counter
is cleared when the framer has successfully obtained synchronization at the CRC4 level. The counter can
also be cleared by disabling the CRC4 mode (CCR1.0=0). This counter is useful for determining the
amount of time the framer has been searching for synchronization at the CRC4 level.
ITU G.706
suggests that if synchronization at the CRC4 level cannot be obtained within 400 ms, then the search
should be abandoned and proper action taken. The CRC4 Sync Counter will rollover.