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参数资料
| 型号： | DS21Q58LN |
| 英文描述： | E1 Quad Transceiver |
| 中文描述： | 素E1通道收发器 |
| 文件页数： | 12/74页 |
| 文件大小： | 647K |
| 代理商： | DS21Q58LN |
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DS21Q58 E1 Quad Transceiver
12 of 74
4.1 Pin Function Descriptions
Table 4-3. System (Backplane) Interface Pins
NAME
TYPE
FUNCTION
TCLK
I
Transmit Clock.
TCLK is a 2.048MHz primary clock that is used to clock data through the transmit
formatter.
Transmit Serial Data.
Transmit NRZ serial data. TSER is sampled on the falling edge of TCLK when
IBO is disabled. It is sampled on the falling edge of SYSCLK when the IBO function is enabled.
Transmit Sync.
As an input, a pulse at this pin establishes either frame or multiframe boundaries for the
transmitter. As an output, it can be programmed to output either a frame or multiframe pulse.
Receive Serial Data.
RSER is the received NRZ serial data. RSER is updated on the rising edges of
RCLK when the receive elastic store is disabled. It is updated on the rising edges of SYSCLK when the
receive elastic store is enabled.
Receive Sync.
An extracted pulse one RCLK wide is output at this pin that identifies either frame or
CAS/CRC4 multiframe boundaries. If the receive elastic store is enabled, this pin can be enabled to be
an input at which a frame-boundary pulse synchronous with SYSCLK is applied.
System Clock.
SYSCLK is a 2.048MHz clock used to clock data out of the receive elastic store. When
the IBO is enabled SYSCLK can be a 4.096MHz, 8.192MHz, or 16.384MHz clock.
User-Selectable Output A.
OUTA is a multifunction pin the host can program to output various alarms,
clocks, or data, or be used to control external circuitry.
User-Selectable Output B.
OUTB is a multifunction pin the host can program to output various alarms,
clocks, or data, or be used to control external circuitry.
TSER
I
TSYNC
I/O
RSER
O
RSYNC
I/O
SYSCLK
I
OUTA
O
OUTB
O
Table 4-4. Alternate Jitter Attenuator
NAME
TYPE
FUNCTION
AJACKI
AJACKO
I
O
Alternate Jitter Attenuator Clock Input.
AJACKI is clock input to the alternate jitter attenuator.
Alternate Jitter Attenuator Clock Output.
AJACKO is clock output of the alternate jitter attenuator.
Table 4-5. Clock Synthesizer
NAME
TYPE
FUNCTION
4/8/16MCK
O
4.096MHz/8.192MHz/16.384MHz Clock Output.
4/8/16MCK is a 4.096MHz, 8.192MHz, or 16.384MHz
clock output that is referenced to one of the four recovered line clocks (RCLKs) or to an external
2.048MHz reference.
Reference Clock.
REFCLK can be configured as an output to source a 2.048MHz reference clock or as
an input to supply a 2.048MHz reference clock from an external source to the clock synthesizer.
REFCLK
I/O
Table 4-6. Parallel Port Control Pins
NAME
TYPE
FUNCTION
INT
O
Interrupt.
INT
flags the host controller during conditions and change of conditions defined in status
registers 1 and 2 and the HDLC status register. It is an active-low, open-drain output.
Bus Type Select Bit 0.
BTS0 is used with BTS1 to select between muxed, nonmuxed, serial bus
operation, and output high-Z mode.
Bus Type Select Bit 1.
BTS1 is used with BTS0 to select between muxed, nonmuxed, serial bus
operation, and output high-Z mode.
Transceiver Select Bit 0.
TS0 is used with TS1 to select one of four transceivers.
Transceiver Select Bit 1.
TS1 is used with TS0 to select one of four transceivers.
Parallel Bus Type Select.
PBTS is used to select between Motorola and Intel parallel bus types.
Data Bus or Address/Data Bus [D0 to D6], Data Bus or Address/Data Bus [D7]/Serial Port Output.
In nonmultiplexed bus operation (MUX = 0), these pins serve as the data bus. In multiplexed bus
operation (MUX = 1), they serve as an 8-bit multiplexed address/data bus.
Address Bus.
In nonmultiplexed bus operation, these pins serve as the address bus. In multiplexed bus
operation, these pins are not used and should be wired low.
Read Input—Data Strobe/Serial Port Clock.
RD
and
DS
are active-low signals. DS is active high when
in multiplexed mode (Section
26
).
Chip Select.
CS
must be low to read or write to the device. It is an active-low signal
.
Address Latch Enable (Address Strobe) or A6.
In nonmultiplexed bus operation, this pin serves as the
upper address bit. In multiplexed bus operation, it demultiplexes the bus on a positive-going edge.
Write Input (Read/Write)/Serial Port Data Input, Active Low
BTS0
I
BTS1
I
TS0
TS1
PBTS
I
I
I
AD0 to
AD7/SDO
I/O
A0 to A4
I
RD
(
DS
)/SCLK
I
CS
I
ALE (AS)/A5
I
WR
(R/
W
)
/
SDI
I
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相关代理商/技术参数 |
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| DS21Q58LN+ | 功能描述:网络控制器与处理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21Q59 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:RELIABILITY REPORT FOR DS21Q59, REV A2 |
| DS21Q59DK | 功能描述:网络开发工具 DS21Q59 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V |
| DS21Q59L | 功能描述:网络控制器与处理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21Q59L+ | 功能描述:网络控制器与处理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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