- 您现在的位置：买卖IC网 > PDF目录378591 > DS21Q58LN E1 Quad Transceiver PDF资料下载
参数资料
| 型号： | DS21Q58LN |
| 英文描述： | E1 Quad Transceiver |
| 中文描述： | 素E1通道收发器 |
| 文件页数： | 13/74页 |
| 文件大小： | 647K |
| 代理商： | DS21Q58LN |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页当前第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页
DS21Q58 E1 Quad Transceiver
13 of 74
Table 4-7. Serial Port Control Pins
NAME
TYPE
FUNCTION
SDO
SDI
ICES
OCES
SCLK
O
I
I
I
I
Serial Port Data Output.
Data at this output can be updated on the rising or falling edge of SCLK.
Serial Port Data Input.
Data at this input can be sampled on the rising or falling edge of SCLK.
Input Clock-Edge Select.
ICES is used to select which SCLK clock edge samples data at SDI.
Output Clock-Edge Select.
OCES is used to select which SCLK clock edge updates data at SDO.
Serial Port Clock.
SCLK is used to clock data into and out of the serial port.
Table 4-8. Line Interface Pins
NAME
TYPE
FUNCTION
MCLK
I
Master Clock Input.
A 2.048MHz (±50ppm) clock source with TTL levels is applied at this pin. This clock
is used internally for both clock/data recovery and for jitter attenuation.
Receive Tip and Ring.
RTIP and RRING are analog inputs for clock recovery circuitry. These pins
connect through a 1:1 step-up transformer to the E1 line. See Section
21
for details.
Transmit Tip and Ring.
TTIP and TRING are analog line-driver outputs. These pins connect through a
1:2 step-up transformer to the E1 line. See Section
21
for details.
RTIP and
RRING
TTIP and
TRING
I
O
Table 4-9. Supply Pins
NAME
DVDD
RVDD
TVDD
DVSS
RVSS
TVSS
TYPE
Supply
Supply
Supply
Supply
Supply
Supply
FUNCTION
Digital Positive Supply.
3.3V ±5%. Should be wired to the RVDD and TVDD pins.
Receive Analog Positive Supply.
3.3V ±5%. Should be wired to the DVDD and TVDD pins.
Transmit Analog Positive Supply.
3.3V ±5%. Should be wired to the RVDD and DVDD pins.
Digital Signal Ground.
0V. Should be wired to the RVSS and TVSS pins.
Receive Analog Signal Ground.
0V. Should be wired to DVSS and TVSS.
Transmit Analog Signal Ground.
0V. Should be wired to DVSS and RVSS.
5. FUNCTIONAL DESCRIPTION
The analog AMI/HDB3 waveform off the E1 line is transformer-coupled into the DS21Q58’s RRING and RTIP pins.
The device recovers clock and data from the analog signal and passes it through the jitter attenuation mux to the
receive framer, where the digital serial stream is analyzed to locate the framing/multiframe pattern. The DS21Q58
contains an active filter that reconstructs the analog-received signal for the nonlinear losses that occur in
transmission. The device has a usable receive sensitivity of 0dB to -12dB. The receive framer locates FAS frame
and CRC and CAS multiframe boundaries as well as detects incoming alarms including carrier loss, loss of
synchronization, AIS, and remote alarm. If needed, the receive elastic store can be enabled to absorb the phase
and frequency differences between the recovered E1 data stream and an asynchronous backplane clock, which is
provided at the SYSCLK input. The clock applied at the SYSCLK input can be either a
2.048MHz/4.096MHz/8.192MHz or 16.384MHz clock. The transmit framer is independent of the receive framer in
both the clock requirements and characteristics. The transmit formatter provides the necessary frame/multiframe
data overhead for E1 transmission.
Note:
This data sheet assumes a particular nomenclature of the E1 operating environment. In each 125 s frame,
there are 32 8-bit time slots numbered 0 to 31. Time slot 0 is transmitted first and received first. These 32 time slots
are also referred to as channels with a numbering scheme of 1 to 32. Time slot 0 is identical to channel 1, time slot
1 is identical to channel 2, and so on. Each time slot (or channel) is made up of eight bits that are numbered 1 to 8.
Bit number 1, MSB, is transmitted first. Bit number 8, the LSB, is transmitted last. The term “locked” is used to refer
to two clock signals that are phase-locked or frequency-locked or derived from a common clock (i.e., an 8.192MHz
clock can be locked to a 2.048MHz clock if they share the same 8kHz component).
相关PDF资料 |
PDF描述 |
|---|---|
| DS21Q58 | Dallas Semiconductor |
| DS2227-70 | Flexible NV SRAM Stik |
| DS2227-100 | Flexible NV SRAM Stik |
| DS2227-120 | Flexible NV SRAM Stik |
| DS2227 | Flexible NV SRAM Stik |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS21Q58LN+ | 功能描述:网络控制器与处理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21Q59 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:RELIABILITY REPORT FOR DS21Q59, REV A2 |
| DS21Q59DK | 功能描述:网络开发工具 DS21Q59 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V |
| DS21Q59L | 功能描述:网络控制器与处理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21Q59L+ | 功能描述:网络控制器与处理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
发布紧急采购，3分钟左右您将得到回复。