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| 型号： | DS21Q58LN |
| 英文描述： | E1 Quad Transceiver |
| 中文描述： | 素E1通道收发器 |
| 文件页数： | 51/74页 |
| 文件大小： | 647K |
| 代理商： | DS21Q58LN |
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DS21Q58 E1 Quad Transceiver
51 of 74
Figure 21-4. Transmit Waveform Template
21.4 Jitter Attenuators
The DS21Q58 contains an on-board clock and data jitter attenuator for each transceiver and a single, undedicated
“clock only” jitter attenuator. This undedicated jitter attenuator is shown in the block diagram (
Figure 3-1
) as the
alternate jitter attenuator.
21.4.1 Clock and Data Jitter Attenuators
The clock and data jitter attenuators can be mapped into the receive or transmit paths and set to buffer depths of
either 32 or 128 bits through the LICR. The 128-bit mode is used in applications where large excursions of wander
are expected. The 32-bit mode is used in delay-sensitive applications. The characteristics of the attenuators are
shown in
Figure 21-6
. The jitter attenuators can be placed in either the receive path or the transmit path by
appropriately setting or clearing the JAS bit in the LICR. Also, setting the DJA bit in the LICR can disable the jitter
attenuator (in effect, remove it). For the jitter attenuator to operate properly, a 2.048MHz clock (±50ppm) must be
applied at the MCLK pin. On-board circuitry adjusts either the recovered clock from the clock/data recovery block or
the clock applied at the TCLK pin to create a smooth jitter-free clock that is used to clock data out of the jitter
attenuator FIFO. It is acceptable to provide a gapped/bursty clock at the TCLK pin if the jitter attenuator is placed
on the transmit side. If the incoming jitter exceeds either 120UI
P-P
(buffer depth is 128 bits) or 28UI
P-P
(buffer depth
is 32 bits), the DS21Q58 divides the internal nominal 32.768MHz clock by either 15 or 17 instead of the normal 16
to keep the buffer from overflowing. When the device divides by either 15 or 17, it also sets the jitter attenuator limit
trip (JALT) bit in the receive information register (RIR.5).
0
-0.1
-0.2
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0
TIME (ns)
S
50
100
150
200
250
-50
-100
-150
-200
-250
269ns
194ns
219ns
(
i
G.703
TEMPLATE
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PDF描述 |
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| DS21Q58 | Dallas Semiconductor |
| DS2227-70 | Flexible NV SRAM Stik |
| DS2227-100 | Flexible NV SRAM Stik |
| DS2227-120 | Flexible NV SRAM Stik |
| DS2227 | Flexible NV SRAM Stik |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS21Q58LN+ | 功能描述:网络控制器与处理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21Q59 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:RELIABILITY REPORT FOR DS21Q59, REV A2 |
| DS21Q59DK | 功能描述:网络开发工具 DS21Q59 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V |
| DS21Q59L | 功能描述:网络控制器与处理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21Q59L+ | 功能描述:网络控制器与处理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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