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| 型号： | DS31256+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 120/183页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR HDLC 256-CHANNEL 256BGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 40 |
| 控制器类型： | HDLC 控制器 |
| 接口： | 串行 |
| 电源电压： | 3 V ~ 3.6 V |
| 电流 - 电源： | 500mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-BBGA |
| 供应商设备封装： | 256-BGA（27x27） |
| 包装： | 管件 |
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DS31256 256-Channel, High-Throughput HDLC Controller
41 of 183
Bit 8/Status Bit for Receive DMA Small Buffer Read (RSBR). This status bit is set to 1 each time the receive
DMA completes a single read or a burst read of the small buffer free queue. The RSBR bit is cleared when read
and is not set again until another read of the small buffer free queue has occurred. If enabled through the RSBR bit
in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus
through the
PINTA signal pin and also at the LINT if the local bus is in configuration mode.
Bit 9/Status Bit for Receive DMA Small Buffer Read Error (RSBRE). This status bit is set to 1 each time the
receive DMA tries to read the small buffer free queue and it is empty. The RSBRE bit is cleared when read and is
not set again until another read of the small buffer free queue detects that it is empty. If enabled through the
RSBRE bit in the interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI
bus through the
PINTA signal pin and also at the LINT if the local bus is in configuration mode.
Bit 10/Status Bit for Receive DMA Done-Queue Write (RDQW). This status bit is set to 1 when the receive
DMA writes to the done queue. Based of the setting of the receive done-queue threshold setting (RDQT0 to
RDQT2) bits in the receive DMA queues-control (RDMAQ) register, this bit is set either after each write or after a
programmable number of writes from 2 to 128 (Section 9.2.4). The RDQW bit is cleared when read and is not set
again until another write to the done queue has occurred. If enabled through the RDQW bit in the interrupt mask
for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the
PINTA signal
pin and also at the
LINT if the local bus is in configuration mode.
Bit 11/Status Bit for Receive DMA Done-Queue Write Error (RDQWE). This status bit is set to 1 each time
the receive DMA tries to write to the done queue and it is full. The RDQWE bit is cleared when read and is not set
again until another write to the done queue detects that it is full. If enabled through the RDQWE bit in the interrupt
mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the
PINTA
signal pin and also at the
LINT if the local bus is in configuration mode.
Bit 12/Status Bit for Transmit FIFO Underflow (TUDFL). This status bit is set to 1 if any of the HDLC
channels experiences an underflow in the transmit FIFO. The TUDFL bit is cleared when read and is not set again
until another underflow has occurred. If enabled through the TUDFL bit in the interrupt mask for SDMA
(ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the
PINTA signal pin and also
at the
LINT if the local bus is in configuration mode.
Bit 13/Status Bit for Transmit DMA Pending-Queue Read (TPQR). This status bit is set to 1 each time the
transmit DMA reads the pending queue. The TPQR bit is cleared when read and is not set again until another read
of the pending queue has occurred. If enabled through the TPQR bit in the interrupt mask for SDMA (ISDMA),
the setting of this bit causes a hardware interrupt at the PCI bus through the
PINTA signal pin and also at the LINT
if the local bus is in configuration mode.
Bit 14/Status Bit for Transmit DMA Done-Queue Write (TDQW). This status bit is set to 1 when the transmit
DMA writes to the done queue. Based on the setting of the transmit done-queue threshold setting (TDQT0 to
TDQT2) bits in the transmit DMA queues-control (TDMAQ) register, this bit is set either after each write or after
a programmable number of writes from 2 to 128 (Section 9.2.4). The TDQW bit is cleared when read and is not set
again until another write to the done queue has occurred. If enabled through the TDQW bit in the interrupt mask
for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the
PINTA signal
pin and also at the
LINT if the local bus is in configuration mode.
Bit 15/Status Bit for Transmit DMA Done-Queue Write Error (TDQWE). This status bit is set to 1 each time
the transmit DMA tries to write to the done queue and it is full. The TDQWE bit is cleared when read and is not
set again until another write to the done queue detects that it is full. If enabled through the TDQWE bit in the
interrupt mask for SDMA (ISDMA), the setting of this bit causes a hardware interrupt at the PCI bus through the
PINTA signal pin and also at the LINT if the local bus is in configuration mode.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS31256+ | 功能描述:输入/输出控制器接口集成电路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 产品: 输入/输出端数量: 工作电源电压: 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-64 封装:Tray |
| DS31256B | 功能描述:输入/输出控制器接口集成电路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 产品: 输入/输出端数量: 工作电源电压: 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-64 封装:Tray |
| DS31256DK | 功能描述:网络开发工具 RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V |
| DS31256-W+ | 制造商:Maxim Integrated Products 功能描述:ENVOY 256 CHANNEL HDLC - WAIVER - Rail/Tube |
| DS312BNC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Industrial Control IC |
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