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参数资料
| 型号： | DS31256+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 158/183页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR HDLC 256-CHANNEL 256BGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 40 |
| 控制器类型： | HDLC 控制器 |
| 接口： | 串行 |
| 电源电压： | 3 V ~ 3.6 V |
| 电流 - 电源： | 500mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-BBGA |
| 供应商设备封装： | 256-BGA（27x27） |
| 包装： | 管件 |
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DS31256 256-Channel, High-Throughput HDLC Controller
76 of 183
8.1.1 Receive High Watermark
The high watermark tells the device how many blocks the HDLC engines should write into the receive
FIFO before the DMA sends data to the PCI bus, or rather, how full the FIFO should get before it should
be emptied by the DMA. When the DMA begins reading the data from the FIFO, it reads all available
data and tries to completely empty the FIFO even if one or more EOFs (end of frames) are detected. For
example, if four blocks were link-listed together and the host programmed the high watermark to three
blocks, then the DMA would read the data out of the FIFO and transfer it to the PCI bus after the HDLC
controller had written three complete blocks in succession into the FIFO and still had one block left to
fill. The DMA would not read the data out of the FIFO again until another three complete blocks had
been written into the FIFO in succession by the HDLC engine or until an EOF was detected. In this
example of four blocks being link-listed together, the high watermark could also be set to 1 or 2, but no
other values would be allowed. If an incoming packet does not fill the FIFO enough to reach the high
watermark before an EOF is detected, the DMA still requests that the data be sent to the PCI bus; it does
not wait for additional data to be written into the FIFO by the HDLC engines.
8.1.2 Transmit Low Watermark
The low watermark tells the device how many blocks should be left in the FIFO before the DMA should
begin getting more data from the PCI bus, or rather, how empty the FIFO should get before it should be
filled again by the DMA. When the DMA begins reading the data from the PCI bus, it reads all available
data and tries to completely fill the FIFO even if one or more EOFs (HDLC packets) are detected. For
example, if five blocks were link-listed together and the host programmed the low watermark to two
blocks, then the DMA would read the data from the PCI bus and transfer it to the FIFO after the HDLC
engine has read three complete blocks in succession from the FIFO and, therefore, still had two blocks
left before the FIFO was empty. The DMA would not read the data from the PCI bus again until another
three complete blocks had been read from the FIFO in succession by the HDLC engines. In this example
of five blocks being link-listed together, the low watermark could also be set to any value from 1 to 3
(inclusive) but no other values would be allowed. In other words, the tranmist low watermark can be set
to a value of 1 to N - 2, where N = number of blocks linked together. When a new packet is written into a
completely empty FIFO by the DMA, the HDLC engines wait until the FIFO fills beyond the low
watermark or until an EOF is seen before reading the data out of the FIFO.
8.2 FIFO Register Description
Register Name:
RFSBPIS
Register Description:
Receive FIFO Starting Block Pointer Indirect Select
Register Address:
0900h
Bit #
7
6
5
4
3
2
1
0
Name
HCID7
HCID6
HCID5
HCID4
HCID3
HCID2
HCID1
HCID0
Default
0
Bit #
15
14
13
12
11
10
9
8
Name
IAB
IARW
n/a
Default
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 7/HDLC Channel ID (HCID0 to HCID7)
00000000 (00h) = HDLC channel number 1
11111111 (FFh) = HDLC channel number 256
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS31256+ | 功能描述:输入/输出控制器接口集成电路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 产品: 输入/输出端数量: 工作电源电压: 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-64 封装:Tray |
| DS31256B | 功能描述:输入/输出控制器接口集成电路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 产品: 输入/输出端数量: 工作电源电压: 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-64 封装:Tray |
| DS31256DK | 功能描述:网络开发工具 RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V |
| DS31256-W+ | 制造商:Maxim Integrated Products 功能描述:ENVOY 256 CHANNEL HDLC - WAIVER - Rail/Tube |
| DS312BNC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Industrial Control IC |
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