参数资料
型号: DS31256+
厂商: Maxim Integrated Products
文件页数: 9/183页
文件大小: 0K
描述: IC CTRLR HDLC 256-CHANNEL 256BGA
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 40
控制器类型: HDLC 控制器
接口: 串行
电源电压: 3 V ~ 3.6 V
电流 - 电源: 500mA
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 256-BBGA
供应商设备封装: 256-BGA(27x27)
包装: 管件
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DS31256 256-Channel, High-Throughput HDLC Controller
106 of 183
Table 9-G. Transmit DMA Main Operational Areas
DESCRIPTORS
FUNCTION
SECTION
Packet
A dedicated area of memory that describes the location and attributes of the
packet data.
Pending Queue
A dedicated area of memory that the host writes to inform the DMA that
packet data is queued and ready for transmission.
Done Queue
A dedicated area of memory that the DMA writes to inform the host that the
packet data has been transmitted.
Host Linking of Data Buffers
As previously mentioned, the data buffers are limited to a length of 8188 Bytes. If an outgoing packet
requires more memory space than the available data buffer contains, the host can link multiple data
buffers together to handle a packet length of any size. The host does this through the end-of-frame (EOF)
bit in the packet descriptor. Each data buffer has a one-to-one association with a packet descriptor. If the
host wants to link multiple data buffers together, the EOF bit is set to 0 in all but the last data buffer.
Figure 9-10 shows an example for HDLC channel 5 where the host has linked three data buffers
together. The transmit DMA knows where to find the next data buffer when the EOF bit is set to 0
through the next descriptor pointer field.
Host Linking of Packets (Packet Chaining)
The host also has the option to link multiple packets together in a chain. Through the chain valid (CV)
bit in the packet descriptor, the host can inform the transmit DMA that the next descriptor pointer field
contains the descriptor of another HDLC packet that is ready for transmission. The transmit DMA
ignores the CV bit until it sees EOF = 1, which indicates the end of a packet. If CV = 1 when EOF = 1,
this indicates to the transmit DMA that it should use the next descriptor pointer field to find the next
packet in the chain. Figure 9-12 shows an example of packet chaining. Each column represents a separate
packet chain. In column 1, three data buffers have been linked together by the host for packet #1, and the
host has created a packet chain by setting CV = 1 in the last descriptor of packet #1.
DMA Linking of Packets (Horizontal Link Listing)
The transmit DMA also has the ability to link packets together. Internally, the transmit DMA can store
up to two packet chains, but if the host places more packet chains into the pending queue, the transmit
DMA must begin linking these chains together externally. The transmit DMA does this by writing to
packet descriptors (Figure 9-12). If columns 1 and 2 were the only two packet chains queued for
transmission, then the transmit DMA would not need to link packet chains together, but as soon as
column 3 was queued for transmission, the transmit DMA had to store the third chain externally because
it had no more room internally. The transmit DMA links the packet chain in the third column to the one
in the second column by writing the first descriptor of the third chain in the next pending descriptor
pointer field of the first descriptor of the second column (it also sets the PV bit to 1). As shown in the
figure, this chaining was carried one step farther to link the fourth column to the third.
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DS31256+ 功能描述:输入/输出控制器接口集成电路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 产品: 输入/输出端数量: 工作电源电压: 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-64 封装:Tray
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DS31256DK 功能描述:网络开发工具 RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V
DS31256-W+ 制造商:Maxim Integrated Products 功能描述:ENVOY 256 CHANNEL HDLC - WAIVER - Rail/Tube
DS312BNC 制造商:未知厂家 制造商全称:未知厂家 功能描述:Industrial Control IC