参数资料
型号: DS31256+
厂商: Maxim Integrated Products
文件页数: 148/183页
文件大小: 0K
描述: IC CTRLR HDLC 256-CHANNEL 256BGA
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 40
控制器类型: HDLC 控制器
接口: 串行
电源电压: 3 V ~ 3.6 V
电流 - 电源: 500mA
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 256-BBGA
供应商设备封装: 256-BGA(27x27)
包装: 管件
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页当前第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页
DS31256 256-Channel, High-Throughput HDLC Controller
67 of 183
7. HDLC
7.1 General Description
The DS31256 contains two different types of HDLC controllers. Each port has a slow HDLC engine
(type #1) associated with it that can operate in either a channelized mode up to 8.192Mbps or an
unchannelized mode at rates up to 10Mbps. Ports 0 and 1 also have an additional fast HDLC engine
(type #2) that can operate in only an unchannelized fashion up to 52Mbps. Through the Layer 1 registers
(Section 6.2), the host determines which type of HDLC controller is used on a port and if the HDLC
controller is to be operated in either a channelized or unchannelized mode. If the HDLC controller is to
be operated in the channelized mode, then the Layer 1 registers (Section 6.3) also determine which
HDLC channels are associated with which DS0 channels. If the fast HDLC engine is enabled on port 0,
HDLC channel 1 is assigned to it and, likewise, HDLC channel 2 is assigned to the fast HDLC engine on
port 1 if it is enabled.
The HDLC controllers can handle all required normal real-time tasks. Table 7-B lists all the functions
supported by the receive HDLC and Table 7-C lists all the functions supported by the transmit HDLC.
Each of the 256 HDLC channels within the DS31256 are configured by the host through the receive
HDLC channel definition (RHCD) and transmit channel definition (THCD) registers. There is a separate
RHCD and THCD register for each HDLC channel. The host can access the RHCD and THCD registers
indirectly through the RHCDIS indirect select and THCDIS indirect select registers. See Section 7.2 for
details.
On the receive side, one of the outcomes shown in Table 7-A occurs when the HDLC block is processing
a packet. For each packet, one of these outcomes is reported in the receive done-queue descriptor
(Section 9.2.4). On the transmit side, when the HDLC block is processing a packet, an error in the PCI
block (parity or target abort) or transmit FIFO underflow causes the HDLC block to send an abort
sequence (eight 1s in a row) followed continuously by the selected interfill (either 7Eh or FFh) until the
HDLC channel is reset by the transmit DMA block (Section 9.3.1). This same sequence of events will
occur even if the transmit HDLC channel is being operated in the transparent mode. In the transparent
mode, when the FIFO empties the device sends either 7Eh or FFh.
If any of the 256 receive HDLC channels detects an abort sequence, an FCS checksum error, or if the
packet length was incorrect, then the appropriate status bit in SDMA is set. If enabled, the setting of any
of these statuses can cause a hardware interrupt to occur. See Section 5.3.2 for details about the operation
of these status bits.
Table 7-A. Receive HDLC Packet Processing Outcomes
OUTCOME
CRITERIA
EOF/Normal Packet
Integral number of packets > min and < max is received and CRC is okay
EOF/Bad FCS
Integral number of packets > min and < max is received and CRC is bad
Abort Detected
Seven or more 1s in a row detected
EOF/Too Few Bytes
Fewer than 4 or 6 Bytes received
Too Many Bytes
Greater than the packet maximum is received (if detection enabled)
EOF/Bad # of Bits
Not an integral number of bytes received
FIFO Overflow
Tried to write a byte into an already full FIFO
相关PDF资料
PDF描述
DS3141+ IC FRAMER DS3/E3 SNGL 144CSBGA
DS31412N IC 12CH DS3/3 FRAMER 349-BGA
DS3150TN IC LIU T3/E3/STS-1 IND 48-TQFP
DS3154N+ IC LIU DS3/E3/STS-1 QD 144CSBGA
DS3164+ IC ATM/PACKET PHY QUAD 400-BGA
相关代理商/技术参数
参数描述
DS31256+ 功能描述:输入/输出控制器接口集成电路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 产品: 输入/输出端数量: 工作电源电压: 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-64 封装:Tray
DS31256B 功能描述:输入/输出控制器接口集成电路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 产品: 输入/输出端数量: 工作电源电压: 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-64 封装:Tray
DS31256DK 功能描述:网络开发工具 RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V
DS31256-W+ 制造商:Maxim Integrated Products 功能描述:ENVOY 256 CHANNEL HDLC - WAIVER - Rail/Tube
DS312BNC 制造商:未知厂家 制造商全称:未知厂家 功能描述:Industrial Control IC