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参数资料
| 型号： | DS31256+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 152/183页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR HDLC 256-CHANNEL 256BGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 40 |
| 控制器类型： | HDLC 控制器 |
| 接口： | 串行 |
| 电源电压： | 3 V ~ 3.6 V |
| 电流 - 电源： | 500mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-BBGA |
| 供应商设备封装： | 256-BGA（27x27） |
| 包装： | 管件 |
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DS31256 256-Channel, High-Throughput HDLC Controller
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zero destuffing, and abort detection, octet length checking, or FCS checking. When in transparent mode, the
device must not be configured to write done-queue descriptors only at the end of a packet, if it is desired that done-
queue descriptors be written; there is not an end of packet on the receive side in transparent mode by definition.
Please note that an end of packet does not occur on the receive side while in transparent mode.
0 = transparent mode disabled
1 = transparent mode enabled
Bit 1/Receive Octet Length-Detection Enable (ROLD). When this bit is set low, the HDLC engine does not
check to see if the octet length of the received packets exceeds the count loaded into the receive HDLC packet
length (RHPL) register. When this bit is set high, the HDLC engine checks to see if the octet length of the received
packets exceeds the count loaded into the RHPL register. When an incoming packet exceeds the maximum length,
the packet is aborted and the remainder is discarded. This bit is ignored if the HDLC channel is set to transparent
mode (RTRANS = 1).
0 = octet length detection disabled
1 = octet length detection enabled
Bits 2, 3/Receive CRC Selection (RCRC0/RCRC1). These two bits are ignored if the HDLC channel is set into
transparent mode (RTRANS = 1).
RCRC1
RCRC0
ACTION
0
No CRC verification performed
0
1
16-bit CRC (CCITT/ITU Q.921)
1
0
32-bit CRC
1
Illegal state
Bit 4/Receive Invert Data Enable (RID). When this bit is set low, the incoming HDLC packets are not inverted
before processing. When this bit is set high, the HDLC engine inverts all the data (flags, information fields, and
FCS) before processing the data. The data is not reinverted before passing to the FIFO.
0 = do not invert data
1 = invert all data (including flags and FCS)
Bit 5/Receive Bit Flip (RBF). When this bit is set low, the HDLC engine places the first HDLC bit received in the
lowest bit position of the PCI bus bytes (i.e., PAD[0], PAD[8], PAD[16], PAD[24]). When this bit is set high, the
HDLC controller places the first HDLC bit received in the highest bit position of the PCI bus bytes (i.e., PAD[7],
PAD[15], PAD[23], PAD[31]).
0 = the first HDLC bit received is placed in the lowest bit position of the bytes on the PCI bus
1 = the first HDLC bit received is placed in the highest bit position of the bytes on the PCI bus
Bit 6/Receive CRC Strip Enable (RCS). When this bit is set high, the FCS is not transferred through to the PCI
bus. When this bit is set low, the HDLC engine includes the 2-Byte FCS (16-bit) or 4-Byte FCS (32-bit) in the
data that it transfers to the PCI bus. This bit is ignored if the HDLC channel is set into transparent mode
(RTRANS = 1).
0 = send FCS to the PCI bus
1 = do not send the FCS to the PCI bus
Bit 7/Receive Abort Disable (RABTD). When this bit is set low, the HDLC engine examines the incoming data
stream for the abort sequence, which is seven or more consecutive 1s. When this bit is set high, the incoming data
stream is not examined for the abort sequence, and, if an incoming abort sequence is received, no action is taken.
This bit is ignored when the HDLC controller is configured in the transparent mode (RTRANS = 1).
Bit 8/Receive Zero Destuffing Disable (RZDD). When this bit is set low, the HDLC engine zero destuffs the
incoming data stream. When this bit is set high, the HDLC engine does not zero destuff the incoming data stream.
This bit is ignored when the HDLC engine is configured in the transparent mode (RTRANS = 1).
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS31256+ | 功能描述:输入/输出控制器接口集成电路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 产品: 输入/输出端数量: 工作电源电压: 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-64 封装:Tray |
| DS31256B | 功能描述:输入/输出控制器接口集成电路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 产品: 输入/输出端数量: 工作电源电压: 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-64 封装:Tray |
| DS31256DK | 功能描述:网络开发工具 RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V |
| DS31256-W+ | 制造商:Maxim Integrated Products 功能描述:ENVOY 256 CHANNEL HDLC - WAIVER - Rail/Tube |
| DS312BNC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Industrial Control IC |
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