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参数资料
| 型号： | DS3141+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 22/88页 |
| 文件大小： | 0K |
| 描述： | IC FRAMER DS3/E3 SNGL 144CSBGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 160 |
| 控制器类型： | DS3/E3 调帧器 |
| 接口： | LIU |
| 电源电压： | 3.135 V ~ 3.465 V |
| 电流 - 电源： | 80mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-BGA，CSPBGA |
| 供应商设备封装： | 144-TECSBGA（13x13） |
| 包装： | 托盘 |
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DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers
29 of 88
Register Name:
MSRL
Register Description:
Master Status Register Latched
Register Address:
09h
Bit #
7
6
5
4
3
2
1
0
Name
LORCL
LOTCL
N/A
COVFL
OSTL
Default
—
Note: See Figure 7-4 for details on the interrupt logic for the status bits in the MSRL register.
Bit 0: One-Second Timer Latched (OSTL). This latched status bit is set to 1 on each 1-second boundary, as
timed by the device. The device chooses an arbitrary 1-second boundary that is timed from either the RCLK signal
or the TICLK signal depending on the setting of the OSTCS bit in MC2. OSTL is cleared when the host processor
writes a 1 to it and is not set again until another 1-second boundary has occurred. When OSTL is set, it can cause
a hardware interrupt to occur if the OSTIE bit in the MSRIE register is set to 1. The interrupt is cleared when this bit
is cleared or the interrupt-enable bit is cleared. This bit can be used to determine when to read the error counters, if
the counters are automatically updated by the 1-second timer.
Bit 1: Counter Overflow Event Latched (COVFL). This latched status bit is set to 1 when the COVF status bit in
the MSR register goes high. COVFL is cleared when the host processor writes a 1 to it and is not set again until
COVF goes high again. When COVFL is set, it can cause a hardware interrupt to occur if the COVFIE bit in the
MSRIE register is set to 1. The interrupt is cleared when this bit is cleared or the interrupt-enable bit is cleared. This
bit can be used to determine when a counter overflow event occurs.
Bit 6: Loss-of-Transmit Clock Latched (LOTCL). This latched status bit is set to 1 when the LOTC status bit in
the MSR register goes high. LOTCL is cleared when the host processor writes a 1 to it and is not set again until
LOTC goes high again. When LOTCL is set, it can cause a hardware interrupt to occur if the LOTCIE bit in the
MSRIE register is set to 1. The interrupt is cleared when this bit is cleared or the interrupt-enable bit is cleared. This
bit can be used to determine when a loss of transmit clock event occurs.
Bit 7: Loss-of-Receive Clock Latched (LORCL). This latched status bit is set to 1 when the LORC status bit in
the MSR register goes high. LORCL is cleared when the host processor writes a 1 to it and is not set again until
LORC goes high again. When LORCL is set, it can cause a hardware interrupt to occur if the LORCIE bit in the
MSRIE register is set to 1. The interrupt is cleared when this bit is cleared or the interrupt-enable bit is cleared. This
bit can be used to determine when a loss of receive clock event occurs.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS3141+ | 功能描述:网络控制器与处理器 IC Single DS3/E3 Framer RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS314-1010NR WAF | 制造商:ON Semiconductor 功能描述: |
| DS31412 | 功能描述:网络控制器与处理器 IC 12 Port DS3/E3 Framer RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS31412N | 功能描述:网络控制器与处理器 IC 12 Port DS3/E3 Framer RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS31415 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:3-Input, 4-Output, Single DPLL Timing IC with Sub-ps Output Jitter and 1588 Clock |
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