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参数资料
型号： DS3141+
厂商： Maxim Integrated Products
文件页数： 63/88页
文件大小： 0K
描述： IC FRAMER DS3/E3 SNGL 144CSBGA
产品培训模块： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装： 160
控制器类型： DS3/E3 调帧器
接口： LIU
电源电压： 3.135 V ~ 3.465 V
电流 - 电源： 80mA
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 144-BGA，CSPBGA
供应商设备封装： 144-TECSBGA（13x13）
包装： 托盘
DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers
66 of 88
Register Name:
TFEACA
Register Description:
Transmit FEAC A
Register Address:
64h
Bit #
7
6
5
4
3
2
1
0
Name
N/A
TFCA5
TFCA4
TFCA3
TFCA2
TFCA1
TFCA0
Default
—
0
Bits 0 to 5: Transmit FEAC Codeword A Data (TFCA[5:0]). The FEAC codeword is of the form
…0xxxxxx011111111… where the rightmost bit is transmitted first. TFCA[5:0] are the middle six bits of the second
byte of the FEAC codeword (i.e., the six “x” bits). The transmit FEAC controller can generate two different
codewords. These six bits specify what is to be transmitted for codeword A. TFCA0 is the LSB and is transmitted
first; TFCA5 is the MSB and is transmitted last. The TFS[1:0] control bits determine if this codeword is to be
transmitted. These bits should only be changed when the transmit FEAC controller is in the idle state
(TFS[1:0] = 00).
Register Name:
TFEACB
Register Description:
Transmit FEAC B
Register Address:
65h
Bit #
7
6
5
4
3
2
1
0
Name
N/A
TFCB5
TFCB4
TFCB3
TFCB2
TFCB1
TFCB0
Default
—
0
Bits 0 to 5: Transmit FEAC Codeword B Data (TFCB[5:0]). The FEAC codeword is of the form
…0xxxxxx011111111… where the rightmost bit is transmitted first. TFCB[5:0] are the middle six bits of the second
byte of the FEAC codeword (i.e., the six “x” bits). The transmit FEAC controller can generate two different
codewords. These six bits specify what is to be transmitted for codeword B. TFCB0 is the LSB and is transmitted
first; TFCB5 is the MSB and is transmitted last. The TFS[1:0] control bits determine if this codeword is to be
transmitted. These bits should only be changed when the transmit FEAC controller is in the idle state
(TFS[1:0] = 00).
Register Name:
RFEAC
Register Description:
Receive FEAC
Register Address:
66h
Bit #
7
6
5
4
3
2
1
0
Name
N/A
RFF5
RFF4
RFF3
RFF2
RFF1
RFF0
Default
—
Bits 0 to 5: Receive FEAC FIFO Data (RFF[5:0]). Data from the receive FEAC FIFO can be read from these bits.
The FEAC codeword is of the form …0xxxxxx011111111… where the rightmost bit is received first. These six bits
are the debounced and integrated middle six bits of the second byte of the FEAC codeword (i.e., the six “x” bits).
RFF0 is the LSB and is received first; RFF5 is the MSB and is received last.
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