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参数资料
| 型号： | DS3141+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 49/88页 |
| 文件大小： | 0K |
| 描述： | IC FRAMER DS3/E3 SNGL 144CSBGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 160 |
| 控制器类型： | DS3/E3 调帧器 |
| 接口： | LIU |
| 电源电压： | 3.135 V ~ 3.465 V |
| 电流 - 电源： | 80mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-BGA，CSPBGA |
| 供应商设备封装： | 144-TECSBGA（13x13） |
| 包装： | 托盘 |
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DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers
53 of 88
Register Name:
BBECR1
Register Description:
BERT Bit-Error Counter Register 1 (lower byte)
Register Address:
44h
Bit #
7
6
5
4
3
2
1
0
Name
BEC7
BEC6
BEC5
BEC4
BEC3
BEC2
BEC1
BEC0
Default
0
Register Name:
BBECR2
Register Description:
BERT Bit Error Counter Register 2
Register Address:
45h
Bit #
7
6
5
4
3
2
1
0
Name
BEC15
BEC14
BEC13
BEC12
BEC11
BEC10
BEC9
BEC8
Default
0
Register Name:
BBECR3
Register Description:
BERT Bit Error Counter Register 3 (upper byte)
Register Address:
46h
Bit #
7
6
5
4
3
2
1
0
Name
BEC23
BEC22
BEC21
BEC20
BEC19
BEC18
BEC17
BEC16
Default
0
Bits 0 to 23: BERT Bit-Error Counter (BEC[23:0]). The BBECR registers are loaded with the value of the internal
BERT error counter when the LC control bit in the BCR1 register is toggled. This 24-bit counter increments for each
received data bit that does not match the expected pattern. The error counter starts counting when the BERT goes
into receive synchronization (SYNC = 1) and continues counting even if the BERT loses sync. The error counter
saturates and does not roll over. Upon saturation, the BECO status bit in the BSR register is set. When the LC bit is
toggled, the error count is loaded into the BBECR registers and the internal error counter is cleared. If the BERT is
in sync when LC is toggled, the error counter continues to count up from zero. If the BERT is out of sync when LC
is toggled, the error counter is held at zero until the BERT regains sync. The host processor should toggle LC after
the BERT has synchronized and then toggle LC again when the error-checking period is complete. If the framer
loses synchronization during this period, then the counting results are suspect.
7.10 HDLC Controller
Each framer contains an on-board HDLC controller with 256-byte buffers in the transmit and receive paths. When
the framer is operated in the DS3 C-Bit Parity mode, the HDLC transmitter and receiver are connected to the three
C-bits in M-subframe 5. When the framer is operated in the E3 mode, the user has the option to connect the HDLC
transmitter to the Sn bit, while the HDLC receiver is always connected to the Sn bit in the receive data. If the host
processor does not wish to use the HDLC controller for the Sn bit, then the status provided by the HDLC controller
should be ignored. On the transmit side, the host processor selects the source of the Sn bit through the E3SnC0
and E3SnC1 controls bits in the T3E3CR1 register. The HDLC controller is not used in the DS3 M23 mode.
7.10.1 Receive Operation
On reset, the receive HDLC controller flushes the receive FIFO and begins searching for a new incoming HDLC
packet. It then performs a bit-by-bit search for an HDLC packet and when one is detected, it zero destuffs the
incoming data stream, automatically byte aligns to it, and places the incoming bytes into the receive FIFO as they
are received. The first byte of each packet is marked in the receive FIFO by setting the opening byte (OBYTE) bit.
Upon detecting a closing flag, the receive HDLC controller checks the 16-bit CRC to see if the packet is valid or not
and then marks the last byte of the packet in the receive FIFO by setting the closing byte (CBYTE) bit. The CRC is
not passed to the receive FIFO. When the CBYTE bit is set, the host processor can obtain the status of the
incoming packet through the packet status bits (PS0 and PS1). Incoming packets can be separated by as few as
one flag or by two flags that share a common zero. If the receive FIFO ever fills beyond capacity, the rest of the
incoming packet data is discarded, and the receive FIFO overrun (ROVRL) status bit is set. If such a scenario
occurs, then the last packet in the FIFO is suspect and should be discarded. When an overflow occurs, the receive
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相关代理商/技术参数 |
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|---|---|
| DS3141+ | 功能描述:网络控制器与处理器 IC Single DS3/E3 Framer RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS314-1010NR WAF | 制造商:ON Semiconductor 功能描述: |
| DS31412 | 功能描述:网络控制器与处理器 IC 12 Port DS3/E3 Framer RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS31412N | 功能描述:网络控制器与处理器 IC 12 Port DS3/E3 Framer RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS31415 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:3-Input, 4-Output, Single DPLL Timing IC with Sub-ps Output Jitter and 1588 Clock |
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