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参数资料
| 型号： | DS3254DK |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 13/71页 |
| 文件大小： | 0K |
| 描述： | KIT DEMO FOR DS3254 |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 设计资源： | DS3254DK Gerber Files |
| 标准包装： | 1 |
| 主要目的： | 电信，线路接口单元（LIU） |
| 已用 IC / 零件： | DS3254 |
| 已供物品： | 板，CD |
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DS3251/DS3252/DS3253/DS3254
20 of 71
Register Name:
SRLn
Register Description:
Status Register Latched
Register Address:
04h, 14h, 24h, 34h
Bit
7
6
5
4
3
2
1
0
Name
JAFL
JAEL
TDML
PRBSL
PBERL
RCVL
RLOLL
RLOSL
Default
0
Bit 7: Jitter Attenuator Full Latched (JAFL). This latched status bit is set to one when the jitter attenuator buffer
is full. JAFL is cleared when the host processor writes a one to it and is not set again until the full condition clears
and the buffer becomes full again. When JAFL is set, it can cause a hardware interrupt to occur if the JAFIE
interrupt-enable bit in the SRIE register is set to one. The interrupt is cleared when JAFL is cleared or JAFIE is set
to zero.
Bit 6: Jitter Attenuator Empty Latched (JAEL). This latched status bit is set to one when the jitter attenuator
buffer is empty. JAEL is cleared when the host processor writes a one to it and is not set again until the empty
condition clears and the buffer becomes empty again. When JAEL is set, it can cause a hardware interrupt to occur
if the JAEIE interrupt-enable bit in the SRIE register is set to one. The interrupt is cleared when JAEL is cleared or
JAEIE is set to zero.
Bit 5: Transmitter Driver Monitor Latched (TDML). This latched status bit is set to one when the TDM status bit
changes state (low to high or high to low). TDML is cleared when the host processor writes a one to it and is not set
again until TDM changes state again. When TDML is set, it can cause a hardware interrupt to occur if the TDMIE
interrupt-enable bit in the SRIE register is set to one. The interrupt is cleared when TDML is cleared or TDMIE is
set to zero.
Bit 4: PRBS Detector Output Latched (PRBSL). This latched status bit is set to one when the PRBS status bit
changes state (low to high or high to low). PRBSL is cleared when the host processor writes a one to it and is not
set again until PRBS changes state again. When PRBSL is set, it can cause a hardware interrupt to occur if the
PRBSIE interrupt-enable bit in the SRIE register is set to one. The interrupt is cleared when PRBSL is cleared or
PRBSIE is set to zero.
Bit 3: PRBS Detector Bit Error Latched (PBERL). This latched status bit is set to one when the PRBS detector is
in sync and a bit error has been detected. PBERL is cleared when the host processor writes a one to it and is not
set again until another bit error is detected. When PBERL is set, it can cause a hardware interrupt to occur if the
PBERIE interrupt-enable bit in the SRIE register is set to one. The interrupt is cleared when PBERL is cleared or
PBERIE is set to zero.
Bit 2: Receiver Code Violation Latched (RCVL). This latched status bit is set to one when the RCV status bit in
the SR register goes high. RCVL is cleared when the host processor writes a one to it and is not set again until
RCV goes high again. When RCVL is set, it can cause a hardware interrupt to occur if the RCVIE interrupt-enable
bit in the SRIE register is set to one. The interrupt is cleared when RCVL is cleared or RCVIE is set to zero.
Bit 1: Receiver Loss-of-Clock Lock Latched (RLOLL). This latched status bit is set to one when the RLOL status
bit in the SR register changes state (low to high or high to low). RLOLL is cleared when the host processor writes a
one to it and is not set again until RLOL changes state again. When RLOLL is set, it can cause a hardware
interrupt to occur if the RLOLIE interrupt-enable bit in the SRIE register is set to one. The interrupt is cleared when
RLOLL is cleared or RLOLIE is set to zero.
Bit 0: Receiver Loss-of-Signal Latched (RLOSL). This latched status bit is set to one when the RLOS status bit
in the SR register changes state (low to high or high to low). RLOSL is cleared when the host processor writes a
one to it and is not set again until RLOS changes state again. When RLOSL is set, it can cause a hardware
interrupt to occur if the RLOSIE interrupt-enable bit in the SRIE register is set to one. The interrupt is cleared when
RLOSL is cleared or RLOSIE is set to zero.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS3254N | 功能描述:网络控制器与处理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS3254N# | 功能描述:网络控制器与处理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS3254N+ | 功能描述:网络控制器与处理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS3254NA3 | 制造商:Maxim Integrated Products 功能描述:QUAD ENH DS3/E3 LIU REV A3 IND - Rail/Tube |
| DS3256 | 功能描述:网络控制器与处理器 IC X6 T3/E3 Line Interface Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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