参数资料
型号: DS3254DK
厂商: Maxim Integrated Products
文件页数: 32/71页
文件大小: 0K
描述: KIT DEMO FOR DS3254
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
设计资源: DS3254DK Gerber Files
标准包装: 1
主要目的: 电信,线路接口单元(LIU)
已用 IC / 零件: DS3254
已供物品: 板,CD
DS3251/DS3252/DS3253/DS3254
38 of 71
Early Termination of Bus Transactions. The bus master can terminate SPI bus transactions at any time by
pulling
CS high. In response to early terminations, the DS325x resets its SPI interface logic and waits for the start
of the next transaction. If a write transaction is terminated prior to the SCLK edge that latches the LSB of a data
byte, the current data byte is not written.
Design Option: Wiring SDI and SDO Together. Because communication between the bus master and the
DS325x is half-duplex, the SDI and SDO pins can be wired together externally to reduce wire count. To support
this option, the bus master must not drive the SDI/SDO line when the DS325x is transmitting.
AC Timing. See Table 17-I and Figure 17-5 for AC timing specifications for the SPI interface.
Figure 15-1. SPI Clock Polarity and Phase Options
MSB
LSB
65
4
3
21
CS
SCK
SDI/SDO
CLOCK EDGE USED FOR DATA CAPTURE (ALL MODES)
CPOL = 0, CPHA = 0
CPOL = 0, CPHA = 1
CPOL = 1, CPHA = 0
CPOL = 1, CPHA = 1
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