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参数资料
| 型号： | DS3254DK |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 28/71页 |
| 文件大小： | 0K |
| 描述： | KIT DEMO FOR DS3254 |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 设计资源： | DS3254DK Gerber Files |
| 标准包装： | 1 |
| 主要目的： | 电信，线路接口单元（LIU） |
| 已用 IC / 零件： | DS3254 |
| 已供物品： | 板，CD |
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DS3251/DS3252/DS3253/DS3254
34 of 71
11.
DIAGNOSTICS
11.1 PRBS Generator and Detector
Each LIU has built-in pseudorandom bit sequence (PRBS) generator and detector circuitry for physical layer
testing. The device generates and detects unframed 2
15 - 1 (DS3 or STS-1) or 223 - 1 PRBS, according to the ITU
O.151 specification. To transmit a PRBS pattern, pull the TDSA and TDSB pins high (hardware mode) or set
generator automatically generates 2
15 - 1 for DS3 and STS-1 modes and 223 - 1 for E3 mode.
The PRBS detector, which is always enabled (Table 6-H), reports its status through the PRBS output pin (hardware
and CPU bus modes) or through the PRBS and PBER status bits (CPU bus mode). When the PRBS detector is out
of synchronization, the PRBS pin is forced high. When the detector syncs to an incoming PRBS pattern, the PRBS
pin is driven low, then pulses high, synchronous with RCLK, for each bit error detected. See Figure 11-1 and Figure
11-2 for details. In CPU bus mode, the PRBS status bit is set to one when the detector is out of synchronization
and set to zero when the detector syncs to an incoming PRBS pattern. A change of state of the PRBS bit sets the
PRBSL bit in the SRL register and can also cause an interrupt on the
INT pin if the PRBSIE bit in the SRIE register
is set to one. A pattern bit error set the PBERL bit in the SRL register and can also cause an interrupt if the
PBERIE bit in the SRIE register is set to one.
Figure 11-1. PRBS Output with Normal RCLK Operation
Figure 11-2. PRBS Output with Inverted RCLK Operation
11.2 Loopbacks
Each LIU has three internal loopbacks. See Figure 4-1 and Figure 4-2. The LLB and RLB pins (hardware mode) or
LLB and RLB control bits in the GCR register (CPU bus mode) enable these loopbacks. When LLB = RLB = 0,
loopbacks are disabled. Setting RLB = 1 with LLB = 0 enables remote loopback, which loops recovered clock and
data back through the LIU transmitter. During remote loopback, recovered clock and data are output on RCLK,
RPOS/RDAT, and RNEG/RLCV, but the TPOS/TDAT and TNEG pins are ignored. Setting LLB = 1 with RLB = 0
enables analog local loopback, which loops the outgoing transmit signal back to the receiver’s analog front end.
Setting LLB = RLB = 1 enables digital local loopback, which loops digital transmit clock and data back to the
receiver’s digital circuitry, including the LOS detector, the B3ZS/HDB3 decoder, and the PRBS detector. When
either of the local loopbacks is enabled, the transmit signal is output normally on TXP/TXN, but the received signal
on RXP/RXN is ignored.
PRBS DETECTOR
IS NOT IN SYNC
PRBS DETECTOR IS IN SYNC; THE
PRBS PIN PULSES HIGH FOR EACH BIT
ERROR DETECTED
RCLK
PRBS
RCINV = 0
RCLK
PRBS
PRBS DETECTOR
IS NOT IN SYNC
PRBS DETECTOR IS IN SYNC; THE
PRBS PIN PULSES HIGH FOR EACH BIT
ERROR DETECTED
RCINV = 1
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS3254N | 功能描述:网络控制器与处理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS3254N# | 功能描述:网络控制器与处理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS3254N+ | 功能描述:网络控制器与处理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS3254NA3 | 制造商:Maxim Integrated Products 功能描述:QUAD ENH DS3/E3 LIU REV A3 IND - Rail/Tube |
| DS3256 | 功能描述:网络控制器与处理器 IC X6 T3/E3 Line Interface Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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