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参数资料
| 型号： | DS3254DK |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 21/71页 |
| 文件大小： | 0K |
| 描述： | KIT DEMO FOR DS3254 |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 设计资源： | DS3254DK Gerber Files |
| 标准包装： | 1 |
| 主要目的： | 电信，线路接口单元（LIU） |
| 已用 IC / 零件： | DS3254 |
| 已供物品： | 板，CD |
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DS3251/DS3252/DS3253/DS3254
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9.4 Waveshaping, Line Build-Out, Line Driver
The waveshaping block converts the transmit clock, positive data, and negative data signals into a single AMI
signal with the waveshape required for interfacing to DS3/E3/STS-1 lines. Table 9-A through Table 9-E and Figure
9-1 show the waveform template specifications and test parameters.
Because DS3 and STS-1 signals must meet the waveform templates at the cross-connect through any cable length
from 0 to 450ft, the waveshaping circuitry includes a selectable LBO feature. For cable lengths of 225ft or greater,
the TLBO pin (hardware mode) or the TLBO configuration bit in the TCR register (CPU bus mode) should be low.
When TLBO is low, output pulses are driven onto the coaxial cable without any preattenuation. For cable lengths
less than 225ft, TLBO should be high to enable the LBO circuitry. When TLBO is high, pulses are preattenuated by
the LBO circuitry before being driven onto the coaxial cable. The LBO circuitry provides attenuation that mimics the
attenuation of 225ft of coaxial cable.
The transmitter line driver can be disabled and the TXP and TXN outputs tri-stated by asserting the
TTS input or
the TTS configuration bit in the TCR register. Powering down the transmitter through the TPD configuration bit in
the TCR register (CPU bus mode) also tri-states the TXP and TXN outputs.
9.5 Interfacing to the Line
The transmitter interfaces to the outgoing DS3/E3/STS-1 coaxial cable (75
) through a 2:1 step-down transformer
connected to the TXP and TXN pins. Figure 2-1 shows the arrangement of the transformer and other
recommended interface components. Table 14-A specifies the required characteristics of the transformer.
9.6 Transmit Driver Monitor
The transmit driver monitor compares the amplitude of the transmit waveform to thresholds VTXMIN and VTXMAX. If
the amplitude is less than VTXMIN or greater than VTXMAX for approximately 32 MCLK cycles, then the monitor
activates the
TDM output pin (hardware mode or CPU bus mode) or sets the TDM status bit in the SR register and
optionally activates the
INT output (CPU bus mode). When the transmitter is tri-stated, the transmit driver monitor is
also disabled.
Note that the transmit driver monitor can be affected by reflections caused by shorts and opens on the line. A short
at a distance less than a few inches (~11 inches for FR4 material) can introduce inverted reflections that reduce the
outgoing pulse amplitude below the VTXMIN threshold and thereby activate the TDM pin and/or TDM status bit.
Similarly an open circuit a similar distance away can introduce noninverted reflections that increase the outgoing
amplitude above the VTXMAX threshold and thereby activate TDM and/or TDM. Shorts and opens at larger distances
away from TXP/TXN can also activate
TDM and/or TDM, but this effect is data-pattern dependent.
9.7 Transmitter Power-Down
To minimize power consumption when the transmitter is not being used, assert the TPD configuration bit in the
TCR register (CPU bus mode only). When the transmitter is powered down, the TXP and TXN pins are put in a
high-impedance state and the transmit amplifiers are powered down.
9.8 Transmitter Jitter Generation (Intrinsic)
The transmitter meets the jitter generation requirements of all applicable standards, with or without the jitter
attenuator enabled.
9.9 Transmitter Jitter Transfer
Without the jitter attenuator enabled in the transmit side, the transmitter passes jitter through unchanged. With the
jitter attenuator enabled in the transmit side, the transmitter meets the jitter transfer requirements of all applicable
telecommunication standards in Table 1-A. See Figure 10-1.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS3254N | 功能描述:网络控制器与处理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS3254N# | 功能描述:网络控制器与处理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS3254N+ | 功能描述:网络控制器与处理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS3254NA3 | 制造商:Maxim Integrated Products 功能描述:QUAD ENH DS3/E3 LIU REV A3 IND - Rail/Tube |
| DS3256 | 功能描述:网络控制器与处理器 IC X6 T3/E3 Line Interface Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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