EP1S30F780I6N (Altera) PDF资料下载 Datasheet(314/864 页)

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型号：	EP1S30F780I6N
厂商：	Altera
文件页数：	314/864页
文件大小：	0K
描述：	IC STRATIX FPGA 30K LE 780-FBGA
产品培训模块：	Three Reasons to Use FPGA's in Industrial Designs
产品变化通告：	Package Height Change 03/March/2008
标准包装：	18
系列：	Stratix®
LAB/CLB数：	3247
逻辑元件/单元数：	32470
RAM 位总计：	3317184
输入/输出数：	597
电源电压：	1.425 V ~ 1.575 V
安装类型：	表面贴装
工作温度：	-40°C ~ 100°C
封装/外壳：	780-BBGA
供应商设备封装：	780-FBGA（29x29）

Altera Corporation

July 2005

Stratix Device Handbook, Volume 2

TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices

In true dual-port configuration, the RAM outputs can only be configured

for read-during-write mode. This means that during write operation,

data being written to the A or B port of the RAM flows through to the A

or B outputs, respectively. When the output registers are bypassed, the

new data is available on the rising edge of the same clock cycle it was

written on. For waveforms and information on mixed-port read-during-

Potential write contentions must be resolved external to the RAM because

writing to the same address location at both ports results in unknown

data storage at that location. Data is written on the rising edge of the write

clock for the M-RAM block. For a valid write operation to the same

address of the M-RAM block, the rising edge of the write clock for port A

must occur following the maximum write cycle time interval after the

rising edge of the write clock for port B. Since data is written into the

M512 and M4K blocks at the falling edge of the write clock, the rising

edge of the write clock for port A should occur following half of the

maximum write cycle time interval after the falling edge of the write clock

for port B. If this timing is not met, the data stored in that particular

address is invalid.

See the Stratix Device Family Data Sheet section of the Stratix Device

Handbook, Volume 1 or the Stratix GX Device Family Data Sheet section of

the Stratix GX Device Handbook, Volume 1 for the maximum synchronous

write cycle time.

Figure 2–7 shows true dual-port timing waveforms for write operation at

port A and read operation at port B.

Table 2–11. M-RAM Block Mixed-Port Width Configurations (True Dual-Port)

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