10–4
Altera Corporation
Stratix Device Handbook, Volume 2
July 2005
General Architecture
Stratix and Stratix GX device MultiTrack interconnect resources are
Direct link routing saves row routing resources while providing fast
communication paths between resource blocks. Direct link interconnects
allow an LAB, digital signal processing (DSP) block, or TriMatrixTM
memory block to drive data into the local interconnect of its left and right
neighbors. LABs, DSP blocks, and TriMatrix memory blocks can also use
direct link interconnects to drive data back into themselves for feedback.
The Quartus II software automatically uses these routing resources to
enhance design performance.
f
For more information about LE architecture and the MultiTrack
interconnect structure in Stratix and Stratix GX devices, see the Stratix
Device Family Data Sheet section of the Stratix Device Handbook, Volume 1
or the Stratix GX Device Family Data Sheet section of the Stratix GX Device
Handbook, Volume 1.
DirectDrive Technology
When using APEX II or APE 20K devices, you must place critical paths in
the same MegaLABTM column to improve performance. Additionally, you
should place critical paths in the same MegaLAB structure for optimal
performance. However, this restriction does not exist in Stratix and
Stratix GX devices because they do not contain MegaLAB structures.
With the new DirectDriveTM technology in Stratix and Stratix GX devices,
the actual distance between the source and destination of a path is the
most important criteria for meeting timing performance. DirectDrive
technology ensures that the same routing resources are available to each
design block, regardless of its location in the device.
Table 10–2. Stratix & Stratix GX Device MultiTrack Interconnect Resources
Routing Type
Interconnect
Span
Row
Direct link
Adjacent LABs and/or blocks
Row
R4
Four LAB units horizontally
Row
R8
Eight LAB units horizontally
Row
R24
Horizontal routing across the width of the device
Column
C4
Four LAB units vertically
Column
C8
Eight LAB units vertically
Column
C16
Vertical routing across the length of the device