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| 型号： | EVAL-AD5560EBUZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 22/68页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD5560 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电源监控器/跟踪器/序列发生器 |
| 已用 IC / 零件： | AD5560 |
| 次要属性： | 串行接口 |
| 已供物品： | 板 |
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Data Sheet
AD5560
Rev. D | Page 29 of 68
THEORY OF OPERATION
The AD5560 is a single-channel, device power supply for use
in semiconductor automatic test equipment. All the DAC levels
required to operate the device are available on chip.
This device contains programmable modes to force a pin vol-
tage and measure the corresponding current (FVMI) covering
a wide current measure range of up to ±1.2 A. A voltage sense
amplifier allows measurement of the DUT voltage. Measured
current or voltage is available on the MEASOUT pin.
FORCE AMPLIFIER
The force amplifier is a unity gain amplifier forcing voltage
directly to the device under test (DUT). This high bandwidth
amplifier allows suppression of load transient induced glitching
on the amplifier output. Headroom and footroom requirements
for the amplifier are 2.25 V and an additional ±500 mV dropped
across the selected sense resistor with full-scale current flowing.
The amplifier is designed to drive high currents up to ±1.2 A
with the capability of ganging together outputs of multiple
AD5560 devices for currents in excess of ±1.2 A.
The force amplifier can be compensated to ensure stability
when driving DUT capacitances of up to 160 μF.
The device is capable of supplying transient currents in excess
of ±1.2 A when powering a DUT with a large decoupling
capacitor. A clamp enable pin (CLEN) allows disabling of the
clamp circuitry to allow the amplifier to quickly charge this
large capacitance.
An extra control bit (GPO) is available to switch out DUT
decoupling when making low current measurements.
HW_INH Function
A hardware inhibit pin (HW_INH/LOAD) allows disabling of
the force amplifier, making the output high impedance. This
function is also available through the serial interface (see the
SW-INH bit in the DPS Register 1, Address 0x2).
This pin can also be configured as a LOAD function to allow
multiple devices to be synchronized. Note that either CLEN
or HW_INH can be chosen as a LOAD function.
DAC REFERENCE VOLTAGE (VREF)
One analog reference input, VREF, supplies all DAC levels with
the necessary reference voltage to generate the required dc levels.
OPEN-SENSE DETECT (OSD) ALARM AND CLAMP
The open-sense detect (OSD) circuitry protects the DUT from
overvoltage when the force and sense lines of the force
amplifier becoming disconnected from each other.
This block performs three functions related to the force and
sense lines.
It clamps the sense line to within a programmable
threshold level (plus a VBE) of the force line, where the
programmable threshold is set by the OSD DAC voltage
level. This limits the maximum or minimum voltage that
can appear on the FORCE pin; it can be driven no higher
than [V(FIN DAC) + threshold + VBE] and no lower than
[V(FIN DAC) threshold VBE].
It triggers an alarm on KELALM if the force line goes more
than the threshold voltage away (OSD DAC level) from the
sense line.
It translates the V(force sense) voltage to a level
relative to AGND so that it can be measured through
the MEASOUT pin.
The open-sense detect level is programmable over the range
0.62 V to 5 V (16-bit OSD DAC plus one diode drop). The 5 V
OSD DAC can be accessed through the serial interface (see the
DAC register addressing portion of Table 24). There is a 10 k
resistor that can be connected between the FORCE and SENSE
pins by use of SW11. This 10 k resistor is intended to
maintain a force/sense connection when a DUT is not in place.
It is not intended to be connected when measurements are
being made because this defeats the purpose of the OSD circuit
in identifying an open circuit between FORCE and SENSE. In
addition, the sense path has a 2.5 k resistor in series; there-
fore, if the 10 k switch is closed, errors may become apparent
when in high current ranges.
DEVICE UNDER TEST GROUND (DUTGND)
DUTGND is the ground level of the DUT.
DUTGND Kelvin Sense
KELALM flags when the voltage at the DUTGND pin moves
too far away from the AGND line (>1 V default setting of the
DGS DAC). This alarm trigger is programmable via the serial
interface. The threshold for the alarm function is program-
mable using the DUTGND SENSE DAC (DGS DAC) (see
The DUTGND pin has a 50 μA pull-up resistor that allows
the alarm function to detect whether DUTGND is open. Setting
the disable DUTALM bit high (Register 0x6, Bit 10) disables the
50 μA pull-up resistor and also disables the alarm feature. The
alarm feature can also be set to latched or unlatched (Register 0x6,
Bit 11).
Kelvin Alarm (KELALM)
The open-drain active low Kelvin alarm pin flags the user when
an open occurs in either the sense or DUTGND line; it can be
programmed to be either latched or unlatched (Register 0x6,
Bit 13, Bit 11, Bit 7). The delay in the alarm flag is 50 μs.
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