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| 型号： | EVAL-AD5560EBUZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 37/68页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD5560 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电源监控器/跟踪器/序列发生器 |
| 已用 IC / 零件： | AD5560 |
| 次要属性： | 串行接口 |
| 已供物品： | 板 |
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AD5560
Data Sheet
Rev. D | Page 42 of 68
PACKAGE COMPOSITION AND MAXIMUM
VERTICAL FORCE
The exposed pad and leads of the TQFP package have a 100%
tin finish. The exposed paddle is connected internally to AVSS.
The simulated maximum allowable force for a single lead is
0.18 lbs; total allowable force for the package is 11.5 lbs. The
quoted maximum force may cause permanent lead bending.
Other package failure (die, mold, board) may occur first at
lower forces.
SLEW RATE CONTROL
There are two methods of achieving different slew rates using
the AD5560. One method is using the programmable slew rate
feature that gives eight programmable rates. The second
method is using the ramp feature and an external clock.
Programmable Slew Rate
Eight programmable modes of slew rates are available to choose
from through the serial interface, enabling the user to choose
different rates to power up the DUT. The different slew rates
are achieved by variation in the internal compensation of the
force DAC output amplifier. The slew rates available are
1.000 V/s, 0.875 V/s, 0.750 V/s, 0.625 V/s, 0.5 V/s,
0.4375 V/s, 0.35V s, and 0.313 V/s.
Ramp Function
Included in the AD5560 is a ramp function that enables the
user to apply a rising or falling voltage ramp to the DUT. The
user supplies a clock, RCLK, to control the timing.
This function is controlled via the serial interface and requires
programming of a number of registers to determine the end
value, the ramp size, and the clock divider register to determine
the update rate.
The contents of the FIN DAC x1 register are the ramp start
value. The user must load the end code register and the step
size register. The sign is now generated from the difference
between the FIN DAC x1 register and the end code; then the
step size value is added to or subtracted from FIN DAC x1,
calibrated and stored. The user must supply a clock to the RCLK
pin to load the new code to the DAC. The output settles in 1.2 s
for a step of 10 mV with CDUT in the lowest range of <0.2 F.
While the output is settling, the next step is calculated to be
ready for the next ramp clock. The calibration engine is used
here; therefore, there is a calibration delay of 1.2 s.
The ramp timing is controlled in two ways: by a user-supplied
clock (RCLK) and by a clock divider register. This gives the
user much flexibility over the frequency of the ramp steps. The
ramp typically starts after (2 × clock divider + 2) clocks,
although there can be a ±1 clock delay due to the asynchronous
nature of RCLK. The external clock can be a maximum of 833
kHz when using clock divider = 1. Faster RCLK speeds can be
used, but the fastest ramp rate is linked into the DAC
calibration engine.
For slower ramp rates, an even slower RCLK can be used.
The step sizes are in multiples of 16 LSBs. If the code previous
to the end code is not a multiple of this step size, the last step is
smaller. If the ramp function must be interrupted at any stage
during the ramp, write the interrupt ramp command. The FIN
DAC x1 stops ramping at the current value and returns to
normal operation.
The fastest ramp rate is 0.775 V/s (for a 5 V reference and an
833 kHz clock using a 2032 LSB step size and divider = 1).
The slowest ramp rate is 24 V/s (for a 5 V reference and an
833 kHz clock using a 16 LSB step size and divider = 255).
Even slower ramps can be achieved with slower SCLK. The
ramp continues until any of the following occurs:
It reaches the end code.
An interrupt ramp is received from the user.
If any enabled alarm triggers, the ramp stops to allow
the user to service the activated alarm.
While the device is in ramp mode, the only command that the
interface accepts is an interrupt ramp. No other commands should
be written to the device while ramping because they are ignored.
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