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| 型号： | EVAL-AD7195EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 28/45页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7195 |
| 设计资源： | EVAL-AD7195EBZ Schematic AD7195 Gerber Files |
| 标准包装： | 1 |
| 主要目的： | 接口，模拟前端（AFE） |
| 已用 IC / 零件： | AD7195 |
| 次要属性： | 图形用户界面，USB 接口 |
| 已供物品： | 板 |
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AD7195
Rev. 0 | Page 33 of 44
BRIDGE POWER-DOWN SWITCH
In bridge applications, such as strain gauges and load cells, the
bridge itself consumes the majority of the current in the system.
For example, a 350 Ω load cell requires 15 mA of current when
excited with a 5 V supply. To minimize the current consumption
of the system, the bridge can be disconnected (when it is not
being used) using the bridge power-down switch. Figure 50
shows how the bridge power-down switch is used. The switch
can withstand 30 mA of continuous current, and it has an on
resistance of 10 Ω maximum.
CALIBRATION
The AD7195 provides four calibration modes that can be pro-
grammed via the mode bits in the mode register. These modes
are internal zero-scale calibration, internal full-scale calibration,
system zero-scale calibration, and system full-scale calibration.
A calibration can be performed at any time by setting the MD2
to MD0 bits in the mode register appropriately. A calibration
should be performed when the gain is changed. After each
conversion, the ADC conversion result is scaled using the ADC
calibration registers before being written to the data register.
The offset calibration coefficient is subtracted from the result
prior to multiplication by the full-scale coefficient.
To start a calibration, write the relevant value to the MD2 to
MD0 bits. The DOUT/RDY pin and the RDY bit in the status
register go high when the calibration is initiated. When the
calibration is complete, the contents of the corresponding
calibration registers are updated, the RDY bit in the status
register is reset, the DOUT/ RDY pin returns low (if CS is
low), and the AD7195 reverts to idle mode.
During an internal zero-scale or full-scale calibration, the res-
pective zero input and full-scale input are automatically connected
internally to the ADC input pins. A system calibration, however,
expects the system zero-scale and system full-scale voltages to
be applied to the ADC pins before initiating the calibration
mode. In this way, errors external to the ADC are removed.
From an operational point of view, treat a calibration like
another ADC conversion. A zero-scale calibration, if required,
must always be performed before a full-scale calibration. Set the
system software to monitor the RDY bit in the status register or
the DOUT/RDY pin to determine the end of calibration via a
polling sequence or an interrupt-driven routine.
With chop disabled, both an internal zero-scale calibration and a
system zero-scale calibration require a time equal to the settling
time, tSETTLE, (4/fADC for the sinc4 filter and 3/fADC for the sinc3 filter).
With chop enabled, an internal zero-scale calibration is not
needed because the ADC itself minimizes the offset continuously.
However, if an internal zero-scale calibration is performed, the
settling time, tSETTLE, (2/fADC) is required to perform the calibra-
tion. Similarly, a system zero-scale calibration requires a time of
tSETTLE to complete.
To perform an internal full-scale calibration, a full-scale input
voltage is automatically connected to the selected analog input
for this calibration. For a gain of 1, the time required for an
internal full-scale calibration is equal to tSETTLE. For higher gains,
the internal full-scale calibration requires a time of 2 × tSETTLE.
A full-scale calibration is recommended each time the gain of a
channel is changed to minimize the full-scale error.
A system full-scale calibration requires a time of tSETTLE. With
chop disabled, the zero-scale calibration (internal or system
zero-scale) should be performed before the system full-scale
calibration is initiated.
An internal zero-scale calibration, system zero-scale calibration
and system full-scale calibration can be performed at any output
data rate. An internal full-scale calibration can be performed at
any output data rate for which the filter word FS[9:0] is divisible
by 16, FS[9:0] being the decimal equivalent of the 10-bit word
written to Bit FS9 to Bit FS0 in the mode register. Therefore,
internal full-scale calibrations can be performed at output data
rates such as 10 Hz or 50 Hz when chop is disabled. Using these
lower output data rates results in better calibration accuracy.
The offset error is, typically, 100 μV/gain. If the gain is changed,
it is advisable to perform a calibration. A zero-scale calibration
(an internal zero-scale calibration or system zero-scale
calibration) reduces the offset error to the order of the noise.
The gain error of the AD7195 is factory calibrated at a gain of 1
with a 5 V power supply at ambient temperature. Following this
calibration, the gain error is 0.001%, typically, at 5 V. Table 28
shows the typical uncalibrated gain error for the different gain
settings. An internal full-scale calibration reduces the gain error
to 0.001%, typically, when the gain is equal to 1. For higher
gains, the gain error post internal full-scale calibration is
0.0075%, typically. A system full-sale calibration reduces the
gain error to the order of the noise.
Table 28. Typical Precalibration Gain Error vs. Gain
Gain
Precalibration Gain Error (%)
8
0.11
16
0.20
32
0.23
64
0.29
128
0.39
The AD7195 gives the user access to the on-chip calibration
registers, allowing the microprocessor to read the calibration
coefficients of the device and also to write its own calibration
coefficients from prestored values in the EEPROM. A read of
the registers can be performed at any time. However, the ADC
must be placed in power-down or idle mode when writing to
the registers. The values in the calibration registers are 24-bits
wide. The span and offset of the part can also be manipulated
using the registers.
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