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参数资料
| 型号： | EVAL-AD7195EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 31/45页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7195 |
| 设计资源： | EVAL-AD7195EBZ Schematic AD7195 Gerber Files |
| 标准包装： | 1 |
| 主要目的： | 接口，模拟前端（AFE） |
| 已用 IC / 零件： | AD7195 |
| 次要属性： | 图形用户界面，USB 接口 |
| 已供物品： | 板 |
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AD7195
Rev. 0 | Page 36 of 44
The output data rate is 50 Hz when zero latency is disabled and
12.5 Hz when zero latency is enabled. Figure 31 shows the
frequency response of the sinc4 filter. The filter provides 50 Hz
±1 Hz and 60 Hz ± 1 Hz rejection of 82 dB minimum, assuming
a stable 4.92 MHz master clock.
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
25
50
75
100
125
150
FREQUENCY (Hz)
F
IL
T
E
R
GA
IN
(
d
B
)
08
77
1
-04
4
Figure 31. Sinc4 Filter Response (FS[9:0] = 96, REJ60 = 1)
SINC3 FILTER (CHOP DISABLED)
A sinc3 filter can be used instead of the sinc4 filter. The filter is
selected using the SINC3 bit in the mode register. The sinc3
filter is selected when the SINC3 bit is set to 1.
This filter has good noise performance when operating with
output data rates up to 1 kHz. It has moderate settling time and
moderate 50 Hz/60 Hz (±1 Hz) rejection.
0
87
71
-034
SINC3/SINC4
MODULATOR
ADC
CHOP
Figure 32. Sinc3 Filter (Chop Disabled)
Sinc3 Output Data Rate and Settling Time
The output data rate (the rate at which conversions are available
on a single channel when the ADC is continuously converting)
is equal to
fADC = fCLK/(1024 × FS[9:0])
where:
fADC is the output data rate.
fCLK is the master clock (4.92 MHz nominal).
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
The output data rate can be programmed from 4.7 Hz to
4800 Hz; that is, FS[9:0] can have a value from 1 to 1023.
The settling time is equal to
tSETTLE = 3/fADC
The 3 dB frequency is equal to
f3dB = 0.272 × fADC
Table 31 gives some examples of FS settings and the corres-
ponding output data rates and settling times.
Table 31. Examples of Output Data Rates and the
Corresponding Settling Time
FS[9:0]
Output Data Rate (Hz)
Settling Time (ms)
480
10
300
96
50
60
80
60
50
When a channel change occurs, the modulator and filter reset.
The complete settling time is allowed to generate the first
conversion after the channel change (see Figure 33). Subsequent
conversions on this channel are available at 1/fADC.
CHANNEL
CONVERSIONS
CHANNEL A
CH A
CH B
CHANNEL B
1/
fADC
0
87
71
-0
45
Figure 33. Sinc3 Channel Change
When conversions are performed on a single channel and a step
change occurs, the ADC does not detect the change in analog
input. Therefore, it continues to output conversions at the program-
med output data rate. However, it is at least three conversions later
before the output data accurately reflects the analog input. If the
step change occurs while the ADC is processing a conversion, the
ADC takes four conversions after the step change to generate a fully
settled result.
1/
fADC
ANALOG
INPUT
ADC
OUTPUT
FULLY
SETTLED
0
877
1-
0
46
Figure 34. Asynchronous Step Change in Analog Input
Sinc3 Zero Latency
Zero latency is enabled by setting the single bit (Bit 11) in the
mode register to 1. With zero latency, the complete settling time
is allowed for each conversion. Therefore, the conversion time
when converting on a single channel or when converting on
several channels is constant. The user does not need to consider
the effects of channel changes on the output data rate.
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