参数资料
型号: FDMA1024NZ
厂商: Fairchild Semiconductor
文件页数: 5/8页
文件大小: 0K
描述: MOSFET N-CH DUAL 20V 6-MICROFET
产品目录绘图: MicorFET 2x2, SC-75 Dual
标准包装: 1
系列: PowerTrench®
FET 型: 2 个 N 沟道(双)
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 20V
电流 - 连续漏极(Id) @ 25° C: 5A
开态Rds(最大)@ Id, Vgs @ 25° C: 54 毫欧 @ 5A,4.5V
Id 时的 Vgs(th)(最大): 1V @ 250µA
闸电荷(Qg) @ Vgs: 7.3nC @ 4.5V
输入电容 (Ciss) @ Vds: 500pF @ 10V
功率 - 最大: 700mW
安装类型: 表面贴装
封装/外壳: 6-WDFN 裸露焊盘
供应商设备封装: 6-MicroFET(2x2)
包装: 标准包装
产品目录页面: 1609 (CN2011-ZH PDF)
其它名称: FDMA1024NZDKR
Typical Characteristics T J = 25 °C unless otherwise noted
5
1000
4
I D = 5 A
C iss
3
V DD = 8 V
V DD = 10 V
100
C oss
2
V DD = 12 V
1
0
0
1
2 3 4
Q g , GATE CHARGE (nC)
5
6
10
0.1
f = 1 MHz
V GS = 0 V
1
V DS , DRAIN TO SOURCE VOLTAGE (V)
C rss
10
20
10
Figure 7. Gate Charge Characteristics
-2
10
Figure 8 . Capacitance vs Drain
to Source Voltage
10
10
-3
-4
V GS = 0 V
1
100 us
1 ms
10
-5
T J = 125 o C
THIS AREA IS
LIMITED BY r DS(on)
10 ms
100 ms
10
10
10
-6
-7
-8
0
3
6
9
T J = 25 o C
12
15
0.1
0.01
0.1
SINGLE PULSE
T J = MAX RATED
R θ JA = 173 o C/W
T A = 25 o C
1
10
1 s
10 s
DC
60
V GS, GATE TO SOURCE VOLTAGE (V)
Figure 9. Gate Leakage Current vs Gate to Source
Voltage
V DS , DRAIN to SOURCE VOLTAGE (V)
Figure 10. Forward Bias Safe Operating Area
R θ JA = 173 C/W
T A = 25 C
100
V GS = 4.5 V
10
SINGLE PULSE
o
o
1
10
10
10
10
10
0.3
-3
-2
-1
0
1
100
1000
t, PULSE WIDTH (sec)
Figure 11. Single Pulse Maximum Power Dissipation
?2010 Fairchild Semiconductor Corporation
FDMA1024NZ Rev.B 4
5
www.fairchildsemi.com
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