参数资料
型号: FDMA3028N
厂商: Fairchild Semiconductor
文件页数: 5/7页
文件大小: 0K
描述: MOSFET N-CH 30V DUAL 6MICROFET
标准包装: 3,000
系列: PowerTrench®
FET 型: 2 个 N 沟道(双)
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 30V
电流 - 连续漏极(Id) @ 25° C: 3.8A
开态Rds(最大)@ Id, Vgs @ 25° C: 68 毫欧 @ 3.8A,4.5V
Id 时的 Vgs(th)(最大): 1.5V @ 250µA
闸电荷(Qg) @ Vgs: 5.2nC @ 5V
输入电容 (Ciss) @ Vds: 375pF @ 15V
功率 - 最大: 1.5W
安装类型: 表面贴装
封装/外壳: 6-VDFN 裸露焊盘
供应商设备封装: MicroFET 2x2
包装: 带卷 (TR)
Typical Characteristics T J = 25°C unless otherwise noted
5
4
I D = 3.8 A
V DD = 10 V
500
C iss
V DD = 15 V
3
100
2
V DD = 20 V
C oss
0.1
1
10
1
0
0
1
2
Q g , GATE CHARGE (nC)
3
4
10
f = 1 MHz
V GS = 0 V
V DS , DRAIN TO SOURCE VOLTAGE (V)
C rss
30
Figure 7. Gate Charge Characteristics
20
100
Figure 8. Capacitance vs . Drain
to Source Voltage
10
1
100 μ s
1 ms
10
SINGLE PULSE
R θ JA = 173 o C/W
T A = 25 o C
0.5 -4
10
10
10
THIS AREA IS
LIMITED BY r DS(on)
0.1 SINGLE PULSE
T J = MAX RATED
R θ JA = 173 o C/W
T A = 25 o C
0.01
0.1 1
10
10 ms
100 ms
1 s
10 s
DC
100
1
10
-3
-2
-1
1
10
100
1000
V DS , DRAIN to SOURCE VOLTAGE (V)
Figure 9. Forward Bias Safe
Operating Area
t, PULSE WIDTH (sec)
Figure 10. Single - Pulse Maximum
Power Dissipation
2
1
DUTY CYCLE-DESCENDING ORDER
R θ JA = 173 C/W
0.1
0.01
D = 0.5
0.2
0.1
0.05
0.02
0.01
SINGLE PULSE
o
P DM
t 1
t 2
NOTES:
DUTY FACTOR: D = t 1 /t 2
PEAK T J = P DM x Z θ JA x R θ JA + T A
0.005 -4
10
10
10
10
-3
-2
-1
1
10
100
1000
t, RECTANGULAR PULSE DURATION (sec)
Figure 11. Junction-to-Ambient Transient Thermal Response Curve
?2011 Fairchild Semiconductor Corporation
FDMA3028N Rev.C3
5
www.fairchildsemi.com
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