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参数资料
| 型号： | FX980L6 |
| 厂商： | CML MICROSYSTEMS PLC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 36/86页 |
| 文件大小： | 821K |
| 代理商： | FX980L6 |
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TETRA Baseband Processor
FX980
1997 Consumer Microcircuits Limited
41
D/980/3
TxErrorStatus
Title:
Transmit Error Status register.
Address:
$0x0E
Function:
R
Description:
This register is the Tx Data path error status register. The TxIrqActive bit is set active when one
of the other bits in this register is the source of an interrupt event. All these error conditions are
caused by transitory events, therefore the error condition is latched (marked with an ‘L’).
Reading this status register causes all latched bits to be set inactive, unless an error event is
currently pending.
Setting any bit of this register High will cause an interrupt to be generated (N_IRQ will be set
Low) if the source of the interrupt has not been masked in the corresponding Mask register.
Bit
Name
Active State
Function
7
R
Reserved. Bit value is not defined.
6
TxDataPathQOF
High
RL
Data path gain, phase and offset (GPO) adjustment-unit:
Q channel overflow error status bit.
5
TxDataPathIOF
High
RL
Data path gain, phase and offset (GPO) adjustment-unit:
I channel overflow error status bit.
4
Tx15tapQOF
High
RL
15-tap Q filter data accumulator overflow error status bit.
3
Tx15tapIOF
High
RL
15-tap I filter data accumulator overflow error status bit.
2
Tx49tapOF
High
RL
49-tap I and Q filter data accumulator overflow error status
bit.
1
Tx79tapOF
High
RL
79-tap I and Q filter data accumulator overflow error status
bit.
0
TxIrqActive
High
RL
This bit is set High if there is an active interrupt caused by
one of the status bits in this register.
Address and Data format for TxErrorStatus access
D1 D0
R
D6 D5 D4 D3 D2
Data field [7:0]
Address field [6:0]
1
0
1
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