TETRA Baseband Processor
FX980
1997 Consumer Microcircuits Limited
67
D/980/3
RxDataAccess
Title:
Rx Data path Access point.
Address:
$0x38 to $0x3B (mapped over 4 locations)
Function:
RW
Description:
This register block allows direct access to the Rx Data path values just after the 59-tap (Rx anti-
alias) filter. Both read and write operations are permitted. A read operation reads the signal
values on the I and Q channels. A write operation will write data to the Rx Data path operator
output. To prevent normal Rx data overwriting this value the RxDPAccessSel bit in the
LoopBackCtrl register should be set active. The MSB read data register is buffered to enable
access of a discrete sample value (if this register was not buffered, data from different sample
periods could be in the MSB and LSB registers). Therefore the LSB register must be read first
for correct operation.
Bit
Name
Active State
Function
Address $0x38
7:0
RxDPIDataLSB
Data RW
Least significant 8 bits of the RxDPIData register. This
register must be read before its associated MSB register.
Address $0x39
7:0
RxDPIDataMSB
Data RW
Most significant 8 bits of the RxDPIData register.
Address $0x3A
7:0
RxDPQDataLSB
Data RW
Least significant 8 bits of the RxDPQData register. This
register must be read before its associated MSB register.
Address $0x3B
7:0
RxDPQDataMSB
Data RW
Most significant 8 bits of the RxDPQData register.
Address and Data format for RxDPIData access
D1 D0
D7 D6 D5 D4 D3 D2
D15 D14 D13 D12 D11 D10 D9 D8
0
Data field [15:0]
1
Address field
[6:0]
0
1
0
1
0
1
0
1
Address and Data format for RxDPQData access
D1 D0
D7 D6 D5 D4 D3 D2
D15 D14 D13 D12 D11 D10 D9 D8
0
Data field [15:0]
1
Address field
[6:0]
0
1
0
1
0
1
0
1