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参数资料
| 型号： | FX980L6 |
| 厂商： | CML MICROSYSTEMS PLC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 38/86页 |
| 文件大小： | 821K |
| 代理商： | FX980L6 |
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TETRA Baseband Processor
FX980
1997 Consumer Microcircuits Limited
43
D/980/3
RxErrorStatus
Title:
Receive Error Status register.
Address:
$0x20
Function:
R
Description:
This register is the Rx Data path error status register. The RxIrqActive bit is set active when one
of the other bits in this register is the source of an interrupt event. All these error conditions are
caused by transitory events, therefore the error condition is latched (marked with an ‘L’).
Reading this status register causes all latched bits to be set inactive unless an error event is
currently pending.
Setting any bit of this register High will cause an interrupt to be generated (N_IRQ will be set
Low) if the source of the interrupt has not been masked in the corresponding Mask register.
Bit
Name
Active State
Function
7
RxDataPathQOF
High
RL
Data path gain, phase and offset (GPO) adjustment unit: Q
channel overflow error status bit.
6
RxDataPathIOF
High
RL
Data path gain, phase and offset (GPO) adjustment unit:
I channel overflow error status bit.
5
AdcQOF
High
RL
ADC Q channel overflow error due to excessive input
amplitude.
4
AdcIOF
High
RL
ADC I channel overflow error due to excessive input
amplitude.
3
Rx63tapOF
High
RL
63-tap I and Q filter data accumulator overflow error status
bit.
2
Rx49tapOF
High
RL
49-tap I and Q filter data accumulator overflow error status
bit.
1
EvenSamplePhase
High
RL
When this status bit is active, the associated interrupt may
be used to re-synchronise the Rx data if for any reason
data synchronisation is lost. If the corresponding mask bit
is set inactive, an interrupt will be generated on the next
Q-phase data in the Rx output register. The next falling
edge of SClk with RxFS High indicates the LSB of the Q
channel data. The mask bit should be disabled after this to
prevent continuous Q-phase interrupts.
0
RxIrqActive
High
RL
This bit is set High if there is an active interrupt caused by
one of the status bits in this register.
Address and Data format for RxErrorStatus access
D1 D0
D7 D6 D5 D4 D3 D2
Data field [7:0]
Address field [6:0]
0
1
0
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