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参数资料
| 型号： | FX980L6 |
| 厂商： | CML MICROSYSTEMS PLC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 47/86页 |
| 文件大小： | 821K |
| 代理商： | FX980L6 |
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TETRA Baseband Processor
FX980
1997 Consumer Microcircuits Limited
51
D/980/3
SramData
Title:
I/O access address for the auxiliary DAC1 memories.
Address:
$0x70 to $0x73 (mapped over 4 locations)
Function:
RW
Description:
These four address locations allow access to the 64 x 10 bit SRAM. The contents of this RAM
can be pre-loaded with a table of values which can be automatically sent to auxiliary DAC1 in
either a single cycle or continuous mode, see RamDacCtrl for details. Therefore the RAM can
be used in conjunction with DAC1 to enable user defined profile power ramping of an external
RF power transmitter stage.
The RAM contents are addressed incrementally by first taking the SRamIoEn bit active. While
this bit is inactive the SRam Address Pointer is held reset. The physical address applied to the
RAM is formed from the 4-bit SRam Address Pointer and the two LSB bits from the I/O Access
address (A1,A0). Therefore four locations in the RAM can be accessed by directly addressing
$0x70 to $0x73.
However, accessing location $0x73 post-increments (by a block of four
addresses) the SRam Address Pointer, thus moving the pointer to the next RAM location block.
The 10-bit data word is split between “odd” and “even” locations with the MSB byte in “odd”
addresses (A0 = 1) and 2 LSB’s in “even” addresses.
The SRamIoRdInc bit determines whether a read or a write operation will increment the SRam
Address Pointer. All 16 locations are accessed incrementally, further accesses to this port while
the SRamIoEn bit is active are not valid and may cause data loss.
Bit
Name
Active State
Function
Address $0x70
7:2
RW
Reserved. Set these bits Low. Undefined on read.
1:0
SRamLSBPort0
Data RW
Access port for the LSB register.
Address $0x71
7:0
SRamMSBPort0
Data RW
Access port for the MSB register
Address $0x72
7:2
RW
Reserved. Set these bits Low. Undefined on read.
1:0
SRamLSBPort1
Data RW
Access port for the LSB register.
Address $0x73
7:0
SRamMSBPort3
Data RW
Access port for the MSB register.
Post-increment Sram address pointer.
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