参数资料
型号: GS81302D08E-333
厂商: GSI TECHNOLOGY
元件分类: SRAM
英文描述: 16M X 8 DDR SRAM, 0.45 ns, PBGA165
封装: 15 X 17 MM, 1 MM PITCH, FPBGA-165
文件页数: 13/34页
文件大小: 536K
代理商: GS81302D08E-333
GS81302D08/09/18/36E-375/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2011
20/34
2011, GSI Technology
AC Electrical Characteristics
Parameter
Symbol
-375
-350
-333
-300
-250
Units
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Clock
K, K Clock Cycle Time
C, C Clock Cycle Time
tKHKH
tCHCH
2.66
8.4
2.86
8.4
3.0
8.4
3.3
8.4
4.0
8.4
ns
tKC Variable
tKCVar
0.2
0.2
0.2
0.2
0.2
ns
6
K, K Clock High Pulse Width
C, C Clock High Pulse Width
tKHKL
tCHCL
1.06
1.14
1.2
1.32
1.6
ns
K, K Clock Low Pulse Width
C, C Clock Low Pulse Width
tKLKH
tCLCH
1.06
1.14
1.2
1.32
1.6
ns
K to K High
C to C High
tKHKH
tCHCH
1.13
1.23
1.35
1.49
1.8
ns
K to K High
C to C High
tKHKH
tCHCH
1.13
1.23
1.35
1.49
1.8
ns
K, K Clock High to C, C Clock High
tKHCH
0
1.21
0
1.29
0
1.35
0
1.49
0
1.8
ns
DLL Lock Time
tKCLock
2048
2048
2048
2048
2048
cycle
7
K Static to DLL reset
tKCReset
30
30
30
30
30
ns
Output Times
K, K Clock High to Data Output Valid
C, C Clock High to Data Output Valid
tKHQV
tCHQV
0.45
0.45
0.45
0.45
0.45
ns
4
K, K Clock High to Data Output Hold
C, C Clock High to Data Output Hold
tKHQX
tCHQX
–0.45
–0.45
–0.45
–0.45
–0.45
ns
4
K, K Clock High to Echo Clock Valid
C, C Clock High to Echo Clock Valid
tKHCQV
tCHCQV
0.45
0.45
0.45
0.45
0.45
ns
K, K Clock High to Echo Clock Hold
C, C Clock High to Echo Clock Hold
tKHCQX
tCHCQX
–0.45
–0.45
–0.45
–0.45
–0.45
ns
CQ, CQ High Output Valid
tCQHQV
0.2
0.23
0.25
0.27
0.30
ns
8
CQ, CQ High Output Hold
tCQHQX
–0.2
–0.23
–0.25
–0.27
–0.30
ns
8
CQ Phase Distortion
tCQHCQH
0.9
1.0
1.10
1.24
1.55
ns
K Clock High to Data Output High-Z
C Clock High to Data Output High-Z
tKHQZ
tCHQZ
0.45
0.45
0.45
0.45
0.45
ns
4
K Clock High to Data Output Low-Z
C Clock High to Data Output Low-Z
tKHQX1
tCHQX1
–0.45
–0.45
–0.45
–0.45
–0.45
ns
4
Setup Times
Address Input Setup Time
tAVKH
0.4
0.4
0.4
0.4
0.5
ns
1
Control Input Setup Time (R, W)
tIVKH
0.4
0.4
0.4
0.4
0.5
ns
2
Control Input Setup Time (BWX), (BWX)
tIVKH
0.28
0.28
0.28
0.3
0.35
ns
3
Data Input Setup Time
tDVKH
0.28
0.28
0.28
0.3
0.35
ns
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