GS81302D08/09/18/36E-375/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2011
12/34
2011, GSI Technology
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 175
Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps.
x36 Byte Write Enable (BWn) Truth Table
BW0
BW1
BW2
BW3
D0–D8
D9–D17
D18–D26
D27–D35
1
Don’t Care
0
1
Data In
Don’t Care
1
0
1
Don’t Care
Data In
Don’t Care
0
1
Data In
Don’t Care
1
0
1
Don’t Care
Data In
Don’t Care
0
1
0
1
Data In
Don’t Care
Data In
Don’t Care
1
0
1
Don’t Care
Data In
Don’t Care
0
1
Data In
Don’t Care
1
0
Don’t Care
Data In
0
1
0
Data In
Don’t Care
Data In
1
0
1
0
Don’t Care
Data In
Don’t Care
Data In
0
1
0
Data In
Don’t Care
Data In
1
0
Don’t Care
Data In
0
1
0
Data In
Don’t Care
Data In
1
0
Don’t Care
Data In
0
Data In
x18 Byte Write Enable (BWn) Truth Table
BW0
BW1
D0–D8
D9–D17
1
Don’t Care
0
1
Data In
Don’t Care
1
0
Don’t Care
Data In
0
Data In