- 您现在的位置：买卖IC网 > PDF目录223993 > HY5DU56422ALF-J (HYNIX SEMICONDUCTOR INC) 64M X 4 DDR DRAM, 0.7 ns, PBGA60 PDF资料下载
参数资料
| 型号： | HY5DU56422ALF-J |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | DRAM |
| 英文描述： | 64M X 4 DDR DRAM, 0.7 ns, PBGA60 |
| 封装： | FBGA-60 |
| 文件页数： | 13/36页 |
| 文件大小： | 395K |
| 代理商： | HY5DU56422ALF-J |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页当前第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页
Rev. 0.1/Apr. 02
20
HY5DU56422A(L)F
HY5DU56822A(L)F
HY5DU561622A(L)F
BURST DEFINITION
BURST LENGTH & TYPE
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst
length determines the maximum number of column locations that can be accessed for a given Read or Write com-
mand. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is
reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A 2 -Ai when the burst length
is set to four and by A 3 -Ai when the burst length is set to eight (where Ai is the most significant column address bit
for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location
within the block. The programmed burst length applies to both Read and Write bursts.
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the
burst type and the starting column address, as shown in Burst Definitionon Table
Burst Length
Starting Address (A2,A1,A0)
Sequential
Interleave
2
XX0
0, 1
XX1
1, 0
4
X00
0, 1, 2, 3
X01
1, 2, 3, 0
1, 0, 3, 2
X10
2, 3, 0, 1
X11
3, 0, 1, 2
3, 2, 1, 0
8
000
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
011
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
111
0, 1, 2, 3, 4, 5, 6, 7
7, 6, 5, 4, 3, 2, 1, 0
相关PDF资料 |
PDF描述 |
|---|---|
| HY5MS5B6LF-H | 16M X 16 DDR DRAM, 6.5 ns, PBGA60 |
| HY5PS1G831ALFP-C4 | 128M X 8 DDR DRAM, PBGA68 |
| HY5PS1G831ALFP-Y5 | 128M X 8 DDR DRAM, PBGA68 |
| HY5RS573225AFP-16L | 8M X 32 DDR DRAM, 0.28 ns, PBGA136 |
| HY5V28CF-S | 16M X 8 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HY5DU56422ALT | 制造商:未知厂家 制造商全称:未知厂家 功能描述:64Mx4|2.5V|8K|J/M/K/H/L|DDR SDRAM - 256M |
| HY5DU56422ALT-H | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:256M-S DDR SDRAM |
| HY5DU56422ALT-J | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:256M-S DDR SDRAM |
| HY5DU56422ALT-K | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:256M-S DDR SDRAM |
| HY5DU56422ALT-L | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:256M-S DDR SDRAM |
发布紧急采购，3分钟左右您将得到回复。