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参数资料
| 型号： | HY5DU56422ALF-J |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | DRAM |
| 英文描述： | 64M X 4 DDR DRAM, 0.7 ns, PBGA60 |
| 封装： | FBGA-60 |
| 文件页数： | 23/36页 |
| 文件大小： | 395K |
| 代理商： | HY5DU56422ALF-J |
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DESCRIPTION
The Hynix HY5DU56422, HY5DU56822 and HY5DU561622 are a 268,435,456-bit CMOS Double Data Rate(DDR) Syn-
chronous DRAM, ideally suited for the main memory applications which requires large memory density and high band-
width.
The Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
PRELIMINARY
Rev. 0.1 / Apr. 02
3
HY5DU56422A(L)F
HY5DU56822A(L)F
HY5DU561622A(L)F
VDD, VDDQ = 2.5V +/- 0.2V
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
x16 device has two bytewide data strobes (UDQS,
LDQS) per each x8 I/O
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
On chip DLL align DQ and DQS transition with CK
transition
DM mask write data-in at the both rising and falling
edges of the data strobe
All addresses and control inputs except data, data
strobes and data masks latched on the rising edges
of the clock
Programmable CAS latency 1.5, 2, 2.5 and 3
supported
Programmable burst length 2 / 4 / 8 with both
sequential and interleave mode
Internal four bank operations with single pulsed
/RAS
tRAS Lock-out function supported
Auto refresh and Self refresh supported
8192 refresh cycles / 64ms
60 Ball FBGA Package Type
Full and Half strength driver option controlled by
EMRS
ORDERING INFORMATION
* X means speed grade
Part No.
Configuration
Package
HY5DU56422A(L)F-X*
64Mx4
60 Ball
FBGA
HY5DU56822A(L)F-X*
32Mx8
HY5DU561622A(L)F-X*
16Mx16
OPERATING FREQUENCY
Grade
CL2
CL2.5
Remark
(CL-tRCD-tRP)
- J
133MHz
166MHz
DDR333 (2.5-3-3)
- M
133MHz
DDR266 (2-2-2)
- K
133MHz
DDR266A (2-3-3)
- H
100MHz
133MHz
DDR266B (2.5-3-3)
- L
100MHz
125MHz
DDR200 (2-2-2)
* CL1.5 @ DDR200 supported
* CL3 supported
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PDF描述 |
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| HY5MS5B6LF-H | 16M X 16 DDR DRAM, 6.5 ns, PBGA60 |
| HY5PS1G831ALFP-C4 | 128M X 8 DDR DRAM, PBGA68 |
| HY5PS1G831ALFP-Y5 | 128M X 8 DDR DRAM, PBGA68 |
| HY5RS573225AFP-16L | 8M X 32 DDR DRAM, 0.28 ns, PBGA136 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HY5DU56422ALT | 制造商:未知厂家 制造商全称:未知厂家 功能描述:64Mx4|2.5V|8K|J/M/K/H/L|DDR SDRAM - 256M |
| HY5DU56422ALT-H | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:256M-S DDR SDRAM |
| HY5DU56422ALT-J | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:256M-S DDR SDRAM |
| HY5DU56422ALT-K | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:256M-S DDR SDRAM |
| HY5DU56422ALT-L | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:256M-S DDR SDRAM |
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